Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)

Tanakamaru, Shuhei; Kitamura, Yuta; Yamazaki, Senju; Tokutomi, Tsukasa; Takeuchi, Ken

doi:10.1109/tcsi.2014.2380640

Cited by 11 publications

(4 citation statements)

References 17 publications

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“…Irregular variations are observed in the error ratio, because dominant errors between V TH states are also correlated with the retention-time, W=E cycle and temperature. 22) As noted in Ref. 22, "C" to "B" states error is dominant during shortterm retention.…”

Section: Ber Estimation For Calculating Llrmentioning

confidence: 94%

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Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

Doi¹,

Tokutomi²,

Hachiya³

et al. 2016

Jpn. J. Appl. Phys.

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NAND flash memory’s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose–Chaudhuri–Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Ref’s in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.

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Section: Ber Estimation For Calculating Llrmentioning

confidence: 94%

“…22) As noted in Ref. 22, "C" to "B" states error is dominant during shortterm retention. As a result, "0" to "1" errors are increased in middle page.…”

Section: Ber Estimation For Calculating Llrmentioning

confidence: 94%

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

Doi¹,

Tokutomi²,

Hachiya³

et al. 2016

Jpn. J. Appl. Phys.

Self Cite

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“…Because of its advantages of simple operation and noticeable effect, many researchers have made the in-depth exploration of bit-flip encoding to improve its performance and applicability [7,8,9,10]. Furthermore, the nLC scheme [11], cyclic shift [12], and flash reliability boost Huffman coding [13] also significantly improves the 𝑉 𝑇 𝐻 distributions. In summary, these algorithms sacrifice non-negligible data space to reduce the raw bit error rate (RBER).…”

Section: Introductionmentioning

confidence: 99%

FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme

Zhang

Wang

et al. 2023

IEICE Electron. Express

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With the development of storage technology, NAND Flash's reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC is proposed based on the prediction of the threshold voltage state error rate (VSER) by flag bits. Compared with the conventional scheme, the proposed algorithm extends the data retention time to 25.44 times. The decoding iterations of LDPC are reduced by up to 87.74%.

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“…Flexible-nLC should always work with ECC to reduce the effective BER to below recoverable BER levels. But the ECC encoder and decoder are placed closer to the NAND flash than flexible-nLC since flex-nLC can also 5 / 12 increase the bit-errors by the decoding if the ECC does not first correct the bit-errors during read [14]. Therefore, it can co-exist with any ECC such as advanced soft-information ECC [16].…”

Section: Introductionmentioning

confidence: 99%

A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

Yamazaki

Iwasaki

Hachiya

et al. 2016

Solid-State Electronics

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A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20 years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000 years retention time with 1 W/E cycle. To achieve these requirements, a flexible-nLC scheme is proposed to improve the reliability of 1Xnm TLC NAND flash [1]. The proposed scheme combines two schemes, n-out-of-8 level cell (nLC) [2] and asymmetric coding (AC) [3] with the addition of a vertical flag. By measuring 1Xnm TLC NAND flash memory, the proposed scheme reduces errors by 72% and 69% for digital archive and cold flash respectively, compared to the conventional nLC scheme.

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Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)

Cited by 11 publications

References 17 publications

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme

A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

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