This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories.

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Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively. Data-retention time (Year) Social Networking Service Cold flash Only 1 time write applications A few times updated applications Millennium memory Archive Facebook Twitter Instagram Consumer SSD