Reliability enhancement of 1Xnm TLC for cold flash and millennium memories

Yamazaki, Senju; Tanakamaru, Shuhei; Suzuki, Sakuya; Iwasaki, Takaya; Hachiya, Shogo; Takeuchi, Ken

doi:10.1109/vlsic.2015.7231369

Cited by 4 publications

(3 citation statements)

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“…The narrow V TH margins degrade the reliability because data-retention error and read-disturb error increase. [8][9][10] To reduce these errors, dynamic characteristics of V TH should be evaluated to develop data recovery techniques [11][12][13][14] and advanced error-correcting codes (ECCs). [14][15][16][17][18] As the reliability of NAND flash memory is degraded, low-density parity-check (LDPC) ECC is used due to the high error-correction capability which is close to the theoretical limit.…”

Section: Introductionmentioning

confidence: 99%

Write/erase stress relaxation effect on data-retention and read-disturb errors in triple-level cell NAND flash memory with round-robin wear-leveling

Deguchi¹,

Kobayashi²,

Takeuchi³

2017

Jpn. J. Appl. Phys.

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This study analyzes the influence of the interval of time (t S-P ) between write/erase endurance stress and programming the final data for the dataretention and read-disturb error evaluations in 1X nm triple-level cell (TLC) NAND flash memories. During the interval of time after the write/erase endurance stresses, electrons are de-trapped from the tunnel dielectric. Eventually, the data-retention error decreases in read-"cold" data which is infrequently read. By introducing long t S-P , e.g., 3 h, with round-robin wear-leveling, the bit error rate (BER) of the read-cold data can be decreased by 47%. Moreover, in read-"hot" data which is frequently read, the BER decreases because V TH -down errors are decreased by introducing long t S-P in over 600 read cycles, while the BER does not decrease in case of the smaller read cycles (<600) because V TH -up errors increase during the read operations. This work introduces the mechanism of the V TH -down error in read-"hot" data. The measured BER of the read-hot data decreases by 74% by introducing optimal t S-P with round-robin wear-leveling.

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Section: Introductionmentioning

confidence: 99%

Write/erase stress relaxation effect on data-retention and read-disturb errors in triple-level cell NAND flash memory with round-robin wear-leveling

Deguchi¹,

Kobayashi²,

Takeuchi³

2017

Jpn. J. Appl. Phys.

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“…SSDs are also highly reliable because, unlike hard disk and optical drives, they does not include mechanical components, which might malfunction due to physical wear and tear. Therefore, SSDs are well-suited to store cold data and archive data on enterprise servers, which need 20 and 1000 years retention time, respectively [1].…”

Section: Introductionmentioning

confidence: 99%

“…Whereas the previous work in [1] describes coding scheme optimization based on the data-retention time only, this paper also investigates the optimal coding scheme when 1Xnm TLC NAND flash's W/E cycles, data-retention time and temperature are changed.…”

Section: Introductionmentioning

confidence: 99%

A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

Yamazaki

Iwasaki

Hachiya

et al. 2016

Solid-State Electronics

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A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20 years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000 years retention time with 1 W/E cycle. To achieve these requirements, a flexible-nLC scheme is proposed to improve the reliability of 1Xnm TLC NAND flash [1]. The proposed scheme combines two schemes, n-out-of-8 level cell (nLC) [2] and asymmetric coding (AC) [3] with the addition of a vertical flag. By measuring 1Xnm TLC NAND flash memory, the proposed scheme reduces errors by 72% and 69% for digital archive and cold flash respectively, compared to the conventional nLC scheme.

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Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems

Hsieh

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Reliability enhancement of 1Xnm TLC for cold flash and millennium memories

Cited by 4 publications

References 1 publication

Write/erase stress relaxation effect on data-retention and read-disturb errors in triple-level cell NAND flash memory with round-robin wear-leveling

Write/erase stress relaxation effect on data-retention and read-disturb errors in triple-level cell NAND flash memory with round-robin wear-leveling

A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems

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