Investigation of multi-level-cell and SET operations on super-lattice phase change memories

Abstract

This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories.

Impact of Stoichiometry on the Structure of van der Waals Layered GeTe/Sb2Te3 Superlattices Used in Interfacial Phase‐Change Memory (iPCM) Devices

“…By contrast, in a PCM cell based on a GST alloy, a high RESET current is needed to melt the material prior to amorphization. iPCMs open numerous opportunities for multilevel storage, hybrid devices combining resistive and magnetic memories, logic gate devices, and also devices for THz pulse detection . Incorporation of SLs in iPCM devices by using ULSI microelectronics technology has been demonstrated for large density memory arrays…”

“…[11] Incorporation of SLs in iPCM devices by using ULSI microelectronics technology has been demonstrated for large density memory arrays. [12] Reversible switching between low and high resistance states in vdW layered GeTe/Sb 2 Te 3 SLs has been established by different research groups [5,6,[12][13][14] but the switching mechanism is not elucidated and is currently highly debated. This stems mainly from the lack of information on the structure of the GeTe/Sb 2 Te 3 SLs in the two resistance states.…”

Modeling of switching mechanism in GeSbTe chalcogenide superlattices

“…There have been several suggestions to explain how the atoms are manipulated, including charge injection12, electric field613, magnetic field6, thermal activation7 and polarization dependent optical control14. However, the atomic structures of the low resistance state (LRS) and high resistance states (HRS) are still not fully agreed by different groups, so the atomic mechanism needs further definition.…”

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

“…4 shows measured NRAM single cell set and reset waveforms [21]. NRAM has characteristics of low current and low energy program compared with other emerging memories [8]- [10]. Fig.…”

“…therefore suitable for storage class memory (SCM) [5]- [10]. In prior research works, SSDs that are composed of only SCM (all SCM) and SSDs that mix SCM and NAND (SCM NAND flash hybrid SSD) have demonstrated higher read and write performances compared with the NAND flashbased SSD [11]- [13].…”