Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p&amp;#x002B; poly process integration technologies

Seo, Ji Hun; Han, Kyoung-Rok; Youn, Tae-Un; Heo, Hyeeun; Jang, Sang-Hyun; Kim, Jong-Wook; Yoo, Ho-Nam; Hwang, Joowon; Yang, Cheol–Hoon; Lee, Heeyoul; Kim, Byungkook; Choi, Eun-Seok; Noh, Keum Hwan; Lee, Byoungki; Lee, Byungseok; Chang, Heehyun; Park, Sung-Kye; Ahn, Kun-Ok; Lee, Seokkiu; Kim, Jinwoong; Lee, Seok-Hee

doi:10.1109/iedm.2013.6724554

Cited by 19 publications

(7 citation statements)

References 3 publications

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“…On the other hand, the MLC operation has been widely adopted in planar NAND technology to achieve high density 17 . Recently, some approaches have been proposed to enable 3D vertical NAND technology 18 19 .…”

mentioning

confidence: 99%

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Bai

et al. 2014

Sci Rep

112

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Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >1010 endurance cycles, >104 s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation.

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mentioning

confidence: 99%

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Bai

et al. 2014

Sci Rep

112

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“…For both server applications (standalone NVM) and autonomous connected nodes (embedded NVM), scaling down the technology nodes is a real struggle. NAND flash technology complexity (air gap [8], vertical stacking [9], multiple patterning [10]) and production costs are becoming unaffordable. On the embedded side, NOR flash is facing extremely complex structure [11], and the co-integration with advanced CMOS nodes leads to reliability issues due to the high voltages needed for NVM programming operations.…”

Section: Communication Cost Between Processing Units and Memories Anmentioning

confidence: 99%

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology

Portal

Bocquet

Onkaraiah

et al. 2017

IEEE Trans. Nanotechnology

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Emerging Non-Volatile Memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g. >10 12) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in Micro-Controller Unit (MCU). This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents firstly the HfO 2 based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128kb memory architecture based on RRAM technology and 28nm FDSOI CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle (C2C) variability issue and direct bitcell read access for characterization purpose. The proposed architecture is validated using post-layout simulations on MOS and RRAM corner cases.

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“…In commercial 2D NAND flash memories 10,11,17,18 the distance between FG cells is of the same order as the size of the FG cells. Thus, the interference effects between FG cells are one of the major issues in NAND flash memories 24 .…”

Section: B Interaction Between Fg Cellsmentioning

confidence: 99%

“…The fundamental idea is that we will be able to regard a small FG cell in the single-electron region as a charge qubit. Now the size of the FG NAND flash memory is 15 nm 17,18 , and the size can shrink to beyond 7 nm [19][20][21] . In the flash memory with 15 nm cell, singleelectron effects can be observed at room temperature 22 .…”

Section: Introductionmentioning

confidence: 99%

Quantum Annealing Machine based on Floating Gate Array

Tanamoto,

Higashi,

Marukame

et al. 2017

Preprint

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Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies

Cited by 19 publications

References 3 publications

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology

Quantum Annealing Machine based on Floating Gate Array

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