Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

Abstract

Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >1010 endurance cycles, >104 s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation.

Reconfigurable Memristive Device Technologies

“…As the devices are formed vertically at the electrode sidewalls in this case, a conformal film deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), is required to deposit the switching layers (and any diode or selector layers if needed). Sputtering may be another choice, although its ability to deposit conformal films on high aspect ratio structures is questionable [193], [194]. Alternatively, it is also possible to use angled deposition method in order to get good coverage of the sidewalls with a directional deposition technique [195].…”

“…Alternatively, it is also possible to use angled deposition method in order to get good coverage of the sidewalls with a directional deposition technique [195]. The vertical hole or trench formation can be achieved by either wet etching [189] or dry etching [193], [196] processes, and the verticality of the sidewalls will be essential for cell scalability. The scalability of this approach, however, is not proven.…”

“…Since the device size in VRRAM is determined by the thickness of the horizontal electrode and the width of the vertical pillar electrode, this offers certain benefits for device scaling as controlling the film thickness is easier than controlling the electrode size. The 3-D VRRAM integration could be combined with the multilevel cell concept to further increase the memory density for mass storage application [193].…”

Fully Si compatible SiN resistive switching memory with large self-rectification ratio

“…[1][2][3][4][5][6][7][8] Various resistive materials such as NiO 2 , TiO 2 , HfO 2 , TaO 2 , SiO 2 , Si 3 N 4 , and amorphous Si have been widely reported for applications to RRAM devices as the switching material. [9][10][11][12][13][14][15] Among them, Si 3 N 4 is considered one of the most interesting resistive-switching materials thanks to its abundant defects, which play an important role in resistive switching.…”

Resistive switching characteristics of Si3N4-based resistive-switching random-access memory cell with tunnel barrier for high density integration and low-power applications

“…For an extremely scaled three-dimensional (3-D) RRAM cell, combining a selector device with the cell would be very challending. [12][13][14] In case of integration of a memory cell and a selector in a unit device, the memory density will be directly determined by the total thickness of switching layer and selector. 14 For these reasons, RRAM stack cells are required to have selector function.…”