Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

Wu, Woei-Cherng; Chao, Tien−Sheng; Peng, Wu-Chin; Yang, Wen−Luh; Wang, Jer‐Chyi; Chen, Jianhao; Lai, Chao‐Sung; Yang, Tsung‐Yu; Lee, Chien-Hsing; Hsieh, Tar‐Hwa; Liou, Jhyy Cheng

doi:10.1109/led.2007.891301

Cited by 12 publications

(5 citation statements)

References 13 publications

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“…8,9) Nitride spacer trapping non-volatile memory (NVM) devices have recently emerged as a new type of discrete trapping memory. 10,11) Among them, the spacer-trapping n-type MOSFET with gate-to-source/drain non-overlapped implantation (NOI) has been studied in terms of electrically erasable programmable read-only memory (EEPROM)/ mask read-only memory (MaskROM)/antifuse operations, cycling, retention, scaling, and electron distribution. [11][12][13][14][15] NOI MOSFETs are fully compatible with industrial CMOS fabrications even without modifying the process or increasing mask tooling cost.…”

Section: Introductionmentioning

confidence: 99%

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Jeng¹,

Fan²,

Peng³

et al. 2014

Jpn. J. Appl. Phys.

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The promising use of non-overlapped implantation (NOI) n-type MOSFETs as nonvolatile memory (NVM) devices has received considerable interest owing to their simple device structure and compatibility with logic CMOS processing. In NOI n-type MOSFETs, the charge distribution by channel hot electron injection (CHEI) programming markedly differs from that in other charge trapping devices in terms of electron injection distribution. In this study, hot hole injection (HHI) in NOI NVM devices is investigated using Technology Computer Aided Design (TCAD) simulations, measured program/erase speeds, and charge pumping (CP) techniques. Furthermore, HHI efficiency is theoretically deduced and compared with that of silicon-oxide-nitride-oxide-silicon (SONOS) devices. Similar to the results for SONOS device, the lateral fields by V D biases significantly enhance HHI for erasing NOI devices. However, preprogrammed electrons are also dominant in erasing NOI devices. On the basis of the CP results, the hole distribution by HHI in NOI NVM devices strongly correlates with the distribution of preprogrammed electrons.

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Section: Introductionmentioning

confidence: 99%

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Jeng¹,

Fan²,

Peng³

et al. 2014

Jpn. J. Appl. Phys.

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“…The programmed window can be more than 3 V in less than 1 µs. Furthermore, its novel wrappedsplit-gate structure would also have faster programming speed [11] and more reliable performance [12] than the conventional SONOS cell. A fast and excellent control of the storage charge can be obtained even after large programming disturbance and >10 4 program/erase cycling.…”

Section: Introductionmentioning

confidence: 99%

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Chao

Peng

et al. 2007

Semicond. Sci. Technol.

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In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V TH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

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“…Recently, SONOS (polysilicon-oxide-nitride-oxide-silicon) memory devices are attracting great interest as a possible replacement for the traditional floating-gate flash EEPROM device, due to the low voltage operation [4], simple process integration [5], elimination of drain-induced turn-on [6], and improved cycling endurance [7]. In addition, a SONOS memory device with a split-gate can be fast programmed with low power consumption [8]- [10]. Furthermore, its novel wrapped-split-gate (WSG) structure can also have faster programming speed [9] and more reliable performance [10] than the conventional SONOS cell.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, a SONOS memory device with a split-gate can be fast programmed with low power consumption [8]- [10]. Furthermore, its novel wrapped-split-gate (WSG) structure can also have faster programming speed [9] and more reliable performance [10] than the conventional SONOS cell.…”

Section: Introductionmentioning

confidence: 99%

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The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory

Wang

Chao

et al. 2007

2007 IEEE International Workshop on Memory Technology, Design and Testing

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2-bits/cell operation characteristics of WSG-SONOS memory has been fully studied in different ONO thickness. The 2-bits/cell characteristics of WSG-SONOS memory will be determined by tunneling oxide and total ONO thicknesses. Besides, thicker top oxide thickness will contribute to better gate disturbance performance while maintaining the same drain disturbance. We also found that the excellent endurance can be performed for the device with thinner tunneling oxide thickness. Optimized ONO thickness for WSG-SONOS memory will be demonstrated in this paper.

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Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

Cited by 12 publications

References 13 publications

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory

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