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ABSTRACT:A new 5-GHz CMOS MMIC for a down-conversion structure with an active balun and current-folded mixer is proposed for improving linearity, LO-to-RF isolation, and INTRODUCTIONOne of the critical requirements of modern RF transceivers [1] for portable telecommunication equipment is power consumption, which limits battery lifetime. In general, the best way to reduce power consumption is by reducing the power supply and current. However, due to the effect of transistor noise on the quiescent current, the only way to reduce power consumption in the mixer is by reducing the supply voltage. The conventional Gilbert mixer uses a three-stacked transistor configuration, which is ill-suited for low-voltage use. Therefore, the essence of low-voltage operation depends on reducing the number of stacked transistors and employing a current-folded scheme [2][3][4], which can solve the abovementioned problems. Some research studies [2, 4 -6] have used separate signal amplifiers to drive a Gilbert mixer and a balun transformer has been used to convert the single-ended input to a differential signal for the mixer, which occupies more board space and hence more power is consumed. In this paper, we propose a new CMOS MMIC current-folded mixer with a source-degeneration active balun. The circuit is constructed using a source-degeneration active balun and currentfolded mirror in order to achieve a low-voltage-supply, highlinearity, and cost-effective down-conversion mixer. DESIGN OF THE NEW CMOS MMIC MIXERIn this paper, a conventional active balun stage with source degeneration is applied, as shown in Figure 1. The transconductance G m can be obtained as follows [7,8]:where g m1 , g m2 , and denote the transconductance of M 1 , M 2 , and the body effect of M 2 , respectively. In Eq. (3), if the loadA schematic diagram of the proposed new CMOS MMIC mixer is shown in Figure 2. The circuit uses an active balun with source degeneration to improve the linearity and LO-to-RF isolation, which is constructed by a common source amplifier M 1 , common gate amplifier M 2 and source degeneration resistors R S . Then it cascodes with differential folded mirrors M 3 , M 10 , and M 4 , M 9 , which can reduce the number of series-connected transistors of the Gilbert mixer and result in the current-folded topology so as to achieve low voltage supply. This is followed by a Gilbert quad M 5 -M 8 , and IF output buffer stages M 11 and M 12 . As mentioned above, if we choose a suitable value of R S , then G m will be a weak function of g m1 and g m2 . Therefore, the linearity region of the proposed mixer can be expanded.With a small RF signal v RF , and a large LO signal v LO , as shown in Figure 2, the conversion gain (CG) of the proposed mixer can be calculated as follows. The differential small-signal drain current of M 9 and M 10 is given byWith respect to the Gilbert quad-mixer core [9], the output smallsignal IF current signals are given by Substituting Eqs. (5) and (6) into Eq. (7), the CG becomesLet R S Ͼ Ͼ 1/g m1 , g m1 ϭ g m2 , g m11...

electric field at p-n junction, while for the thick ONO stacks High-performance wrapped-select-gate (WSG) SONGS (60/80/100), the electric field at the gap increased gradually as shown (silicon-oxide-nitride-silicon) memory cells with multi-level and inFig. 5. 2-bit/cell operation have been successfully demonstrated. The Figures 6 and 7 demonstrated the drain and gate disturbance source-side injection mechanism with different ONO thickness in performance of the WSG-SONOS memory with different ONO WSG-SONOS memory was well investigated. The different thickness forthe multi-level operation, respectively. From these figures, programming efficiency of the WSG-SONOS memory with different we can easily observe that the thick top oxide will contribute to better ONO thickness can be explained by the lateral electrical field extracted gate disturbance while the drain disturbance is not affected by the ONO from the simulation. Furthermore, multi-level storage is easily obtained thickness. Moreover, the thin bottom oxide exhibits better P/E cycling and well Vth distribution is also presented. High program/erase speed performance resulted in the VFl shift owing to the less interface states (1Ous/5ms) and low programming current (3.5uA) are performed to generation as indicated in Fig. 8. To sum up, the ONO thickness achieve the multi-level operation with excellent gate and drain (50/80/100) used in the WSG-SONOS memory should be optimized to disturbance, second-bit effect, data retention and endurance.get high performance and better reliability. INTRODUCTION B. MULTI-LEVEL STORAGE Recently, high-density and high-speed programming of flash Figure 9 demonstrates the multi-level operation characteristics of memories is increasingly required. However, much faster programming the WSG-SONOS memory. The ID-VG transfer characteristics and is desired as the chip scale enlarges, since the handling data sizes also excellent distribution of threshold voltage in different programming grow at the same rate [1]. To attain much faster programming, we have states were shown in this Fig. The word line biases were applied 9, 10studied the source-side injection scheme in the novel 2-bit/cell and lIV to achieve the "10", "01" and "00" states (programming time WSG-SONOS memory with different ONO thickness. The optimized is 1 us), while the device was reverse-read at VBL=1.8V. In addition, ONO thickness of WSG-SONOS memory would be observed in this the programming and erasing speed of multi-level operation was shown paper. The high programming speed was easily achieved for multi-level in Fig. 10. The Vth shift is larger than 1, 2 and 3 V at VSG=0.9 V while operation of WSG-SONOS memory with quite low programming the programming time is only 1 us for VWL=9, IO andlIV, respectively. current. Besides, the highly reliable performance of this WSG-SONOS Furthermore, this high programming speed was achieved by quite low memory was also performed in this work programming current smaller than 3.5 uA. Figure II performs the second bit effect characteristics a...