A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM

“…Novel flash cell structures were proposed by researchers to address the severe short channel effects and scalability of standard FG flash memory. In order to surmount critical reliability challenges in device issues that stem from technology scaling, several exploratory and interesting flash cell structures such as FinFET [16][17][18][19]110] and HCFET [15] are studied. Kwak et al have reported that HCFET exhibited excellent enhancement in subthreshold swing and off current when compared to planar type NVM cell structure [15].…”

“…Thus, this shows that HCFET provides superior short channel effects over planar type NVM cell structure [15]. On the other hand, another type of cell structure, namely, FinFET, is also actively under study for its superior reliability performance [16][17][18][19]. Figure 4 shows the TEM cross section of sub-40 nm Bandgap-Engineered (BE) SONOS NVM devices of (a) near planar and (b) FinFET structure [19].…”

“…On the other hand, another type of cell structure, namely, FinFET, is also actively under study for its superior reliability performance [16][17][18][19]. Figure 4 shows the TEM cross section of sub-40 nm Bandgap-Engineered (BE) SONOS NVM devices of (a) near planar and (b) FinFET structure [19]. Implementation of FinFET structure in charge storage NVM devices has shown excellent short channel control characteristics and scalability as compared to planar type cell structure [16][17][18][19].…”

“…Figure 4 shows the TEM cross section of sub-40 nm Bandgap-Engineered (BE) SONOS NVM devices of (a) near planar and (b) FinFET structure [19]. Implementation of FinFET structure in charge storage NVM devices has shown excellent short channel control characteristics and scalability as compared to planar type cell structure [16][17][18][19]. Comparing the near planar structure, FinFET structure shows superior resistance to body effect as well as drain induced barrier lowering (DIBL) effect as a result of the capability of gate control [17,19].…”

“…Many researchers have dedicated their research work on these novel approaches to extend the longevity of charge storage NVM devices beyond 30 nm. These novel approaches include (1) novel flash cell structures [4,[15][16][17][18][19], for example, Hemi-Cylindrical FET (HCFET) and FinFET; (2) new lithography process technologies, for example, improvement in patterning techniques to realize 20 nm structures [20]; (3) novel materials in charge storage layer, for example, phase change memory (PCM) [21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37], magnetic random access memory (MRAM) [6], and nanocrystal ; (4) tunnel barrier engineering, for example, VARIable Oxide Thickness (VARIOT) [60][61][62][63], and implementation of high-k dielectric [64,65], for example, HfO 2 ; (5) enhancement of flash memory system by integrating complex compensation schemes through implementing embedded flash controllers [7]; (6) improvement made on error correction code (ECC) algorithm [7]; and 7innovative way to stack flash cell, for example, high density 3D stack NAND flash and cross point memories. As transistor based charge storage NVM approaching fundamental limits of NVM characteristics soon, these technical solutions or combination of them could be the key in future development of charge storage NVM.…”