Highly Resilient Fault-Tolerant Topology of Single-Phase Multilevel Inverter

Jalhotra, Manik; Sahu, Lalit Kumar; Gupta, Shubhrata; Gautam, Shivam Prakash

doi:10.1109/jestpe.2019.2936271

Cited by 25 publications

(11 citation statements)

References 33 publications

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“…Notably, the FT ability of [22], [31] is achieved by using 4 and 10 relays to bypass the faulty parts, respectively. Furthermore, the structures introduced in [31], [32], and [16] lose voltage levels after multiple switch faults (more than one).…”

Section: B Comparative Studymentioning

confidence: 99%

“…[13]- [15] added a parallel redundant leg to the main module, ensuring a post-fault operation under single and multiple switch faults. Similarly, in [16] an H-bridge is used as a redundant leg in case of fault occurrence. While the number of the generated voltage levels is constant for [14]- [16] after the failure, some voltage levels are lost in single or multiple switch failures in [13].…”

Section: Introductionmentioning

confidence: 99%

“…Similarly, in [16] an H-bridge is used as a redundant leg in case of fault occurrence. While the number of the generated voltage levels is constant for [14]- [16] after the failure, some voltage levels are lost in single or multiple switch failures in [13]. [17] introduced a bypass mechanism to isolate the faulty part and then restores the voltage amplitude by sharing the voltage deficit among other healthy modules.…”

Section: Introductionmentioning

confidence: 99%

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Fault-Tolerant Operation Strategy for Reliability Improvement of a Switched-Capacitor Multilevel Inverter

Hassani

Azimi

Khodaparast

et al. 2022

IEEE Trans. Ind. Electron.

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the necessity of using several components in multilevel inverters jeopardizes the reliability of their operation. Hence, the aim of this research is to propose a novel single-phase fault-tolerant topology based on switched-capacitor concept to ensure robustness of the converter in the occurrence of a fault. The proposed single source converter steps up the input voltage seven times with a simple control strategy. Fault Tolerance of the converter is achieved by considering multiple fault cases and providing several redundant switching schemes concerning the type and location of failure. Each switching scheme is designed in a way to ensure the tolerability to both single and multiple open/short circuit failure. Also, self-voltage balancing of the capacitors, as well as the same amount of voltage levels and amplitude in the output is guaranteed. Experimental analysis is carried out, and the results confirm the viability of the proposed inverter under normal and post-fault operating modes.

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Section: B Comparative Studymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fault-Tolerant Operation Strategy for Reliability Improvement of a Switched-Capacitor Multilevel Inverter

Hassani

Azimi

Khodaparast

et al. 2022

IEEE Trans. Ind. Electron.

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“…The predicted fault class (𝐶𝑙 𝑃 𝑖 ) for the given feature set is determined using the trained classifier as in (9). Then, the predicted class is compared with the actual fault class (𝐶𝑙 𝐴 𝑖 ) to determine the classification accuracy (𝐶𝐴 𝑡 ) in percentage as in (10). The classification accuracy for training (𝐶𝐴 𝑡𝑟 ) and testing data (𝐶𝐴 𝑡𝑒 ) are calculated, and weights added.…”

Section: Figure 9 Objective Function Of Combined Optimizermentioning

confidence: 99%

“…Harmonic reduction in CHBMLI is achieved by increasing the levels, which leads to an increase in power semiconductor switches [9]. It increases the complexity and reduces reliability [10].…”

Section: Introductionmentioning

confidence: 99%

Combined Optimizer for Automatic Design of Machine Learning-Based Fault Classifier for Multilevel Inverters

et al. 2022

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Fault detection and classification are fundamental requirements of multilevel inverters (MLIs) to ensure constant operation and improved reliability. Nowadays, the machine learning (ML) technique is utilized for fault diagnosis in MLIs due to its inherent features such as high accuracy, reduced computation time, and complexity. However, the rich availability of parts and classifiers in ML techniques demands a tedious investigation of every combination to design an optimal fault classifier. To overcome this problem, a combined optimiser is proposed to automate the ML-based classifier design, which involves selecting optimal features and classifier. Mean, total harmonic distortion, root mean square, and different harmonic orders (upto 12 th order) of the output voltage of MLI are considered as features and four different ML techniques like K-nearest neighborhood, decision tree, Naive Bayesian classifier, and support vector machines are considered. Ant Colony Optimization (ACO) is used to formulate a combinatorial optimization routine to maximize classification accuracy by optimal selection of features and classifier. The proposed technique is used to design a fault classifier for two different MLIs, such as Cascaded H-bridge MLI (CHBMLI) and Packed U cell inverter (PUC), during the fault conditions (open circuit and short circuit) to check the feasibility. Simulation results illustrate classification accuracy of 97.84% and 98.61% for CHBMLI and PUC, respectively. Experimental validation of the designed classifier on the inverter prototype is also carried out and illustrates 95.56% and 94.28% classification accuracy for CHBMLI and PUC, respectively.

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State of the Art Resilient Power Converters

2022

Resilient Power Electronic Systems

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Highly Resilient Fault-Tolerant Topology of Single-Phase Multilevel Inverter

Cited by 25 publications

References 33 publications

Fault-Tolerant Operation Strategy for Reliability Improvement of a Switched-Capacitor Multilevel Inverter

Fault-Tolerant Operation Strategy for Reliability Improvement of a Switched-Capacitor Multilevel Inverter

Combined Optimizer for Automatic Design of Machine Learning-Based Fault Classifier for Multilevel Inverters

State of the Art Resilient Power Converters

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