Highly scalable STT-MRAM with MTJs of top-pinned structure in 1T/1MTJ cell

Lee, Young Min; Yoshida, Chikako; Tsunoda, Koji; Umehara, Shinjiro; Aoki, Masaki; Sugii, T.

doi:10.1109/vlsit.2010.5556123

Cited by 21 publications

(11 citation statements)

References 3 publications

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“…The 1T-1MTJ bit-cell design is the most widely-adopted cell design, comprising an MTJ device connected serially with an access transistor [22,23], as shown in Fig. 3(a).…”

Section: T-1mtj Bit-cell Designmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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“…The 1T-1MTJ bit-cell design is the most widely-adopted cell design, comprising an MTJ device connected serially with an access transistor [22,23], as shown in Fig. 3(a).…”

Section: T-1mtj Bit-cell Designmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…ELECTRICAL STT-MRAM MODEL 3 51 MRAM [92], single-level cell (SLC) is predominant in STT-MRAM designs. An SLC STT-MRAM cell stores one bit of data; the bottom-pinned 1T-1MTJ bit cell design is the most widely-adopted SLC design, comprising an MTJ device connected serially with a selector device [93,94], as shown in Figure 3.7a. The MTJ in this structure serves as a storage element, while the selector is responsible for selective access to this cell.…”

Section: Stt-mram Bit Cellmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…STT-MRAMs have several advantages over conventional MRAMs, such as suppression of the increase in current density that accompanies scaling down and reduction in cell area owing to the simplified structure. [14][15][16][17][18][19][20][21][22][23][24] However, STT-MRAMs still have the problem of small on/off resistance ratio, which is one of the biggest obstacles to creating highly integrated memories. Since the improvement of on/off ratio directly depends on the performance of MTJs, the development of MTJs having a large TMR is one of the key issues in realizing highly dense memories such as NAND flash memories.…”

Section: Spin-torque-transfer Mramsmentioning

confidence: 99%

Review of Emerging New Solid-State Non-Volatile Memories

Fujisaki

2013

Jpn. J. Appl. Phys.

114

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The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change randomaccess memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

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Highly scalable STT-MRAM with MTJs of top-pinned structure in 1T/1MTJ cell

Cited by 21 publications

References 3 publications

Defect and Fault Modeling Framework for STT-MRAM Testing

Defect and Fault Modeling Framework for STT-MRAM Testing

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Review of Emerging New Solid-State Non-Volatile Memories

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