Highly selective and low damage atomic layer etching of InP∕InAlAs heterostructures for high electron mobility transistor fabrication

Park, S. D.; Oh, Chaeyoun; Lim, Wontaek; Lee, H. C.; Bae, Jong Woon; Yeom, Geun‐Young; Kim, T. W.; Song, Jong−In; Jang, Jae‐Hyung

doi:10.1063/1.2754636

Cited by 15 publications

(9 citation statements)

References 9 publications

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“…Park et al 69,70 studied ALE of InP and InAlAs based on 20 s exposure to Cl 2 at 0.4 mTorr, followed by Ne neutral beam bombardment. They measured roughly 1 monolayer /cycle (1.47 A/cycle) for InP with high selectivity against InAlAs (0.02 A/cycle), and observed no significant surface compositional changes.…”

Section: Iii-v: Gaasmentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

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The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

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Section: Iii-v: Gaasmentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

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“…The extracted f T (f max ) is 233 GHz (167 GHz) for the ALET device and 203 GHz (175 GHz) for the RIE device. The improvement in f T of the ALET devices is believed to result from the lower plasmainduced damage of the ALET, which was indirectly confirmed by the analysis of the transport property of the p-HEMT structures [11].…”

Section: Resultsmentioning

confidence: 88%

“…Here, the Φ B was extracted using the standard current-voltage (I-V ) technique [13]. The higher Φ B and lower η of the ALET devices are attributed to the lower physical damage of the ALET to the underlying In 0.52 Al 0.48 As barrier [11]. Using angular-resolved X-ray photoelectron spectroscopy, no significant change of the surface composition of the In 0.52 Al 0.48 As barrier layer was observed after the ALET, whereas a significant decrease in the ratios of Al/In and As/InAl was observed in the case of the RIE [11].…”

Section: Methodsmentioning

confidence: 99%

Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As/In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ p-HEMTs

Kim

Duk

et al. 2007

IEEE Electron Device Lett.

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The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In 0.52 Al 0.48 As barrier and showed a much higher etch selectivity (∼70) of the InP spacer against the In 0.52 Al 0.48 As barrier. The 0.15-µm InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G M,max (1.38 S/mm), I ON /I OFF (1.18 × 10 4 ), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (V th,avg = −190 mV and σ = 15 mV), and f T (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area. Index Terms-Atomic layer etching (ALET), drain-induced barrier lowering (DIBL), I ON /I OFF ratio, pseudomorphic highelectron mobility transistor (p-HEMT), subthreshold slope.

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“…The ALET process consisted of four sequential steps; (i) introduction ofCh gas into the etching chamber for 20 s so that the chlorine can be adsorbed on the surface of InP (adsorption step), (ii) evacuation of the Cb gas from the chamber, (iii) Ne neutral beam irradiation to the Ch adsorbed InP surface for desorption of InP chlorides (desorption step), and (iv) evacuation of the InP chlorides from the chamber. Detailed process conditions can be found in [5]- [6]. For comparison, the conventional Ar-based plasma etching was also performed to etch the InP layer with the process pressure of 10 mTorr, the Ar flow of 50 sccm, and the RF power of 7 W in an Oxford Fig.…”

Section: Methodsmentioning

confidence: 99%

“…The damage eventually leads to degradation of Schottky gate and overall device characteristics. Recently, we have successfully demonstrated an Atomic-Layer-ETching (ALET) technology to remove an MBE grown InP layer on a Ino.s2AloAsAs layer [5]. The ALET, which uses low plasma energy, could remove one monolayer of InP per cycle, corresponding to the InP etch rate as slow as 1.47Alcycle and had an extremely high selectivity of 70.…”

Section: Inp-basedmentioning

confidence: 99%

Fabrication of In<inf>0.52</inf>Al<inf>0.48</inf>As/In<inf>0.53</inf>Ga<inf>0.47</inf>As p-HEMT utilizing Ne-based atomic layer etching

Kim¹,

Shin²,

Park

et al. 2008

2008 20th International Conference on Indium Phosphide and Related Materials

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The characteristics of 0.15 Ilm lllo.s2Alo.48AslIllo.s3Gao.47As pseudomorphic high electron mobility transistors (p-HEMTs) fabricated using the Nebased atomic layer etching (ALET) technology and the Arbased conventional reactive ion etching (RIE) technology are reported. Compared to the p-HEMTs fabricated using the Ar-based RIE, the p-HEMTs fabricated using the ALET exhibited improved device performance including trasconductance (G M =I.38 S/mm), IoN/IoFF ratio (1.18X 10 4 ), and cutoff frequency (f T =233 GHz), mainly due to the extremely low plasma-induced damage of the ALET to the Schottky gate area. Keywords-Atomic layer etching (ALET); peudomorphic high electron mobility transistor (p-HEMT), Io,./IoFF ratio I.

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Highly selective and low damage atomic layer etching of InP∕InAlAs heterostructures for high electron mobility transistor fabrication

Cited by 15 publications

References 9 publications

Atomic Layer Etching at the Tipping Point: An Overview

Atomic Layer Etching at the Tipping Point: An Overview

Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As/In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ p-HEMTs

Fabrication of In<inf>0.52</inf>Al<inf>0.48</inf>As/In<inf>0.53</inf>Ga<inf>0.47</inf>As p-HEMT utilizing Ne-based atomic layer etching

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