Atomic layer etching of Si͑100͒ and Si͑111͒ was carried out using Cl 2 adsorption followed by the Ar neutral beam irradiation for the removal of charging damage during the etching. By supplying Cl 2 and Ar neutrals higher than the critical doses, the exact same depth per cycle corresponding to one atomic layer per cycle of 1.36 Å/cycle for silicon ͑100͒ and 1.57 Å/cycle for silicon ͑111͒ could be obtained by a self-limited etching mechanism. The critical Cl 2 pressure and Ar neutral beam irradiation time corresponded to one monolayer chemisorption of chlorine by the dissociative Langmuir isotherm and the irradiation of Ar neutral beam was enough to remove one layer of silicon chloride formed on the silicon surfaces, respectively.Atomic layer etching ͑ALET͒ can be an indispensable method for the fabrication of future devices such as nanoscale devices, quantum devices, etc., 1,2 because current etch technology utilizing reactive ion etching does not have precise etch rate controllability and tends to damage the surface of the devices physically and electrically due to the use of energetic reactive ions to achieve vertical etch profiles.ALET technology has been investigated since the early 1990s for GaAs and Si devices. 3-9 To achieve ALET, many cycles of sequential steps consisting of the adsorption of halogen gas such as chlorine 3-8 or fluorine 9 and the desorption of the formed halide by heat, laser, or Ar + ions are required. For the Si͑100͒ ALET, precise Si etch rates per cycle were obtained by many researchers, however, among the researchers the reported etch rates were different. 1.5-3.0 Å/cycle was reported for the silicon ͑100͒ etching by fluorine gas 9 and 0.68 ϳ 1.36 Å/cycle 6-8 and 0.52 Å/cycle 8 were reported for the silicon ͑100͒ and ͑111͒ etchings by Cl 2 gas, respectively. In addition, for the anisotropic etching of the silicon during the ALET, directional Ar + ions were used in general for the desorption, and which could cause electrical charging damage to the devices similar to that of the conventional reactive ion etching.In fact, the decrease of damage to the semiconductor which occurred during the plasma etching can be obtained by using neutral beam etching instead of conventional reactive ion etching. Figure 1a shows the photoreflectance spectroscopy ͑PRS͒ data of GaAs etched using Cl 2 neutral beam and Cl 2 inductively coupled plasma ͑ICP͒ etching. For comparison, not only the etch depth but also the energy of the neutral beam and the bias voltage of the ICP etching were maintained the same. As shown in the figure, the GaAs etched using the Cl 2 ICP showed the change of the PRS curve compared to nonetched reference GaAs while the GaAs etched using the Cl 2 neutral beam showed a similar PRS curve as the reference. The change of the PRS curve indicates the existence of surface defects, therefore, the surface damage could be decreased significantly by using a neutral beam instead of conventional reactive ion etching. The damage to the gate oxide of metal oxide semiconductor ͑MOS͒ device during t...

Postfabrication rapid thermal annealing ͑RTA͒ and subsequent nitrous oxide ͑N 2 O͒ plasma treatment improved the performance of zinc oxide ͑ZnO͒ thin-film transistors ͑TFTs͒ in terms of off current and on/off current ratio by almost 2 orders of magnitude. The off current of 2 ϫ 10 −8 A and on/off current ratio of 3 ϫ 10 3 obtained after RTA were improved to 10 −10 A and 10 5 , respectively, by the subsequent N 2 O plasma treatment. X-ray photoelectron spectroscopy analysis of the TFT samples showed that the RTAtreated ZnO surface had more oxygen vacancies as compared to as-deposited samples, and the oxygen vacancies at the surface of RTA-treated ZnO were reduced by subsequent N 2 O plasma treatment. The reduction of oxygen vacancies at the top region of the ZnO channel is the cause of better off current and on/off current ratio of the TFTs.Zinc oxide ͑ZnO͒, with a direct bandgap energy of 3.37 eV, is one of the semiconductor materials well suited for transparent thinfilm transistors ͑TFTs͒ in the application areas of active matrix liquid crystal displays ͑AMLCDs͒ and electronic papers. 1-10 However, there are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems facing ZnObased TFTs is high off current ͑leakage current͒ and hence low on/off current ratio. 5-9 Low off current as well as on/off current ratio higher than 10 6 are required for the ZnO TFTs to function as select transistors in AMLCDs. 10 In TFTs with bottom-gate configuration, the drain-to-source current flow through the undepleted channel region as well as the gate-leakage current contribute to the off current. To eliminate the undesired drain-to-source current under the off condition, thinner channel layers have been employed in TFTs. 2,4 However, the crystalline quality of the ZnO materials improves with thickness, so the thinner ZnO channel tends to have more defects, which affects the carrier mobility and subthreshold slope of devices. 1,6 In this work, we studied the effect of postfabrication rapid thermal annealing ͑RTA͒ and subsequent nitrous oxide ͑N 2 O͒ plasma treatment on the off current and on/off current ratio of the fabricated bottom-gated ZnO TFTs. We found that the TFTs subjected to N 2 O plasma treatment exhibit better off current and on/off current ratio. X-ray photoelectron spectroscopy ͑XPS͒ analysis was performed to examine the surface modification of ZnO channel layer due to RTA and N 2 O plasma treatment.Corning 1737 glass coated with 200 nm thick indium tin oxide ͑ITO͒ was used as starting substrates ͑sheet resistance = 4-8 ⍀/Ǣ, Delta Technologies limited, USA͒ for fabricating TFTs with bottomgate configuration, and the ITO acted as the gate electrode. The substrates were ultrasonically cleaned with acetone, methanol, and deionized water. ITO gate electrodes were defined by standard photolithography and wet-etching process using LCE-12k ͑ITO etchant, Cyantek Corporation͒ at 45°C. Next, a 200 nm thick silicon nitride gate-dielectric layer was deposited by plasma-enhanced chemi...

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Highly selective, low damage atomic layer etching ͑ALET͒ technology was developed for dry gate recess during the fabrication of InGaAs/ InP / InAlAs high electron mobility transistors lattice matched to InP substrates. Etching characteristics of InP layer on top of InAlAs layer and the surface chemistry of the exposed InAlAs layer were investigated by utilizing angular resolved x-ray photoelectron spectroscopy. Finally, InAlAs Schottky diodes were fabricated by utilizing chlorine-based ALET technology and conventional Ar-based dry recess and their electrical characteristics were compared. By using the ALET, the etch selectivity as high as 70:1 was achieved for InP over InAlAs heterostructures and the stoichiometric modification of InAlAs was observed to be negligible after the recess etch process. Schottky diodes fabricated after the ALET exhibited the lower ideality factor and the higher Schottky barrier height compared to those fabricated with Ar-based plasma etching.

High electron mobility transistors ͑HEMTs͒ with InAs/ InGaAs composite channel were fabricated by employing low damage, highly selective Ne-based atomic layer etching ͑ALET͒ for the dry gate recess process. Ne-based ALET exhibited very high etch selectivity of InP over InAlAs which is suitable for dry gate recess process removing InP etch stop layer on top of InAlAs Schottky barrier layer. The plasma induced damage on the exposed InAlAs surface due to the ALET was much lower than that due to the conventional Ar-based reactive ion etching ͑RIE͒, which was verified by atomic force microscopy and Hall measurements. For further comparison, dc characteristics were compared for the two types of 0.3 m HEMTs fabricated by utilizing ALET and conventional RIE during the dry gate recess processes.