Host interface design for ATM LANs

Cooper, Eric C.; Menzilcioglu, O.; Sansom, Robert D.; Bitz, Francois

doi:10.1109/lcn.1991.208071

Cited by 29 publications

(8 citation statements)

References 2 publications

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“…The large latency and bandwidth difference between our protocol and both versions of TCP/IP argues strongly in favor of bypassing higher-level protocols whenever possible. The performance disparity supports our decision to build protocols and operating system interfaces from scratch, and confirms earlier predictions that good protocol performance can be obtained with relatively simple hardware [4]. Figure 2 shows the throughput obtained with different message sizes for our three ATM protocol options.…”

Section: Performancesupporting

confidence: 83%

“…All measurements are between two DECstation 5000/200 workstations connected directly by Fore Systems TCA 100 ATM interfaces. 4 Our protocol suite is implemented with about 4i00 lines of C code (not including signaling support). Determining which part of our implementation corresponds to which conceptual protocol layer is difficult because the implementation is integrated.…”

Section: Performancementioning

confidence: 99%

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Simple Protocol Processing fro High-Bandwidth Low-Latency Networking

Brustoloni¹,

Bershad²

1992

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Protocol and operating system overheads have become the limiting factor for communications performance on fast networks such as ATM. A large component of these overheads stems from the protocol redundancy that arises when layering higher level protocols on top of lower level ones. ATM, for example, requires specific mechanisms for connection management, flow control, congestion avoidance, and segmeibation and reassembly. With these mechanisms in place, it is relatively simple and inexpensive to provide for reliable sequenced delivery at the network interface level, making similar functionality in higher-level protocols such as TCP/IP redundant. In this paper we present a protocol architecture specifically tailored for communication over high-bandwidth low-latency local or metropolitan ATM networks. Our architecture yields high performance by eliminating protocol redundancy and by exploiting common-case communication behavior. With this approach, we can combine the functionality typically found in four separate layers of the ISO model --data link through session -in a single pass over the data, delivering high throughput and low latency. Our protocol architecture requires minimal hardware support from the network interface and switch fabric, yet efficiently provides services such as segmentation and reassembly, flow control, congestion avoidance, and error recovery. We have implemented our protocol architecture on a switch-based ATM network consisting of DECstation 5000/200 workstations running the Mach 3.0 operating system. Our implementation achieves latencies and bandwidths close to the physical limitations imposed by the hardware, yet offers applications a high-level reliable transport interface.

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Section: Performancesupporting

confidence: 83%

Section: Performancementioning

confidence: 99%

Simple Protocol Processing fro High-Bandwidth Low-Latency Networking

Brustoloni¹,

Bershad²

1992

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“…This is more significant than the segmentation occurring at the TCPAP and ATM AAL layers, especially for large frame sizes. Since the ATM adapter card is performing on-board segmentation and reassembly (SAR) [4], the cell level segmentation and reassembly is not a performance issue. Differences between the throughputs of TCPAP over ATM, AAL 315 or AAL 5 are a reflection of the additional protocol processing for TCPDP in the host and the AAL 3/4 in the adapter card.…”

Section: A Identifying Pe~ormance Bottlenecksmentioning

confidence: 99%

Supporting real-time and multimedia applications on the Mercuri testbed

Guha

Pavan

Liu

et al. 1995

IEEE J. Select. Areas Commun.

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This paper describes the distributed system, network and software architecture, the application development environment, the performance, and the early lessons learned on the ATM LAN testbed Mercuri established at the Honeywell Technology Center, to develop distributed multimedia technologies for realtime control applications. We have developed a client-serverbased software architecture on Sun Sparcstation-2s connected by a Fore Systems' ASX-100 ATM switch, with video processing handled by Parallax's XVideo cards. The architecture enables network-transparent applications and provides simple primitives for multimedia capture, display, transmission, storage, and retrieval. A real-time multimedia-in-the-loop control application was developed as the vehicle for testing the capabilities and performance of the network. Our test measurements focus on the end-user-level performance metrics such as message throughput and round-trip delay as well as video-frame jitter under no-load and load conditions. Our results show that the maximum burst throughput that can be supported at the user level is 48 Mbls using AAL 5, while round-trip delays for 4-kbyte messages are about 3 ms. Our experience reveals a number of performance bottlenecks and open issues in using commercial ATM switches for practical applications. Our conclusions are: 1) For end-toend performance, the primary bottlenecks are in the protocol processing at layers above ATM (as currently implemented) and the host operating-system's performance for burst data transfers; 2) the current video-processing hardware and its integration with the host operating system are also severe limiting factors; and 3) besides performance issues, other issues that limit ATM for practical application and experimentation are the lack of analysis tools and the support for deadline-driven real-time traffic.

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“…Fore Systems, Inc. [7], and Cambridge University/Olivetti Research [17], have each explored an approach which puts minimal functionality in interface hardware. This approach assigns almost all tasks to the workstation host including ATM adaptation layer processing, e.g., computing checksums, checking segment numbers, etc.…”

Section: Example Host Interface Architecturesmentioning

confidence: 99%

Giving applications access to Gb/s networking

Smith

Traw

1993

IEEE Network

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Network fabrics with Gigabit per second (Gbps) bandwidths are available today, but these bandwidths are not yet available to applications. The difficulties lie in the hardware and software architecture through which application data travels between the network and host memory. The hardware portion of the architecture is often called a host interface and the remainder of the protocol stack is implemented in host software.In this paper, we outline a variety of approaches to the architecture of such systems, examine several design points, and study one example in detail. The detailed example, an ATM Host Interface and Operating System support built at the University of Pennsylvania, illustrates design tradeoffs for hardware and software, and some of the implications of these tradeoffs on applications performance.

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Host interface design for ATM LANs

Cited by 29 publications

References 2 publications

Simple Protocol Processing fro High-Bandwidth Low-Latency Networking

Simple Protocol Processing fro High-Bandwidth Low-Latency Networking

Supporting real-time and multimedia applications on the Mercuri testbed

Giving applications access to Gb/s networking

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