Hot-carrier reliability in submicrometer LDMOS transistors

Versari, R.; Pieracci, A.; Manzini, Stefano; Contiero, C.; Riccò, B.

doi:10.1109/iedm.1997.650402

Cited by 41 publications

(11 citation statements)

References 11 publications

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“…Device-parameter shifts can be reproduced by a degradation model using I b as the driving force [3], [4]. Other studies show that degradation of LDMOS device is correlated to gate current (I g ), and I g maximum stress condition causes the largest device degradation [5], [6]. In this letter, however, experimental data reveal that I b or I g is inadequate to evaluate R on degradation of devices with different n-type driftdrain (NDD) region concentration.…”

Section: Introductionmentioning

confidence: 98%

Effect of Drift-Region Concentration on Hot-Carrier-Induced $R_{\rm on}$ Degradation in nLDMOS Transistors

Chen

Lee

et al. 2008

IEEE Electron Device Lett.

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In this letter, hot-carrier-induced on-resistance (R on ) degradation in lateral DMOS transistors with different n-type drift-drain (NDD) region concentration is investigated. Increasing NDD concentration results in greater bulk (I b ) and gate currents (I g ), but R on degradation is improved. Technology computer-aided design simulations reveal that high NDD concentration increases impact-ionization rate in accumulation (related to I b increase) and channel regions (related to I g increase) but reduces impact-ionization rate in spacer region. Charge-pumping data confirm that hot-carrier-induced interface state created in the spacer region is reduced, leading to improved R on degradation in high-NDD-concentration device.

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Section: Introductionmentioning

confidence: 98%

Effect of Drift-Region Concentration on Hot-Carrier-Induced $R_{\rm on}$ Degradation in nLDMOS Transistors

Chen

Lee

et al. 2008

IEEE Electron Device Lett.

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“…These lateral surface effect devices are, however, susceptible to hot-carrier currents that induce several breakdown mechanisms. Various efforts have been directed towards characterizing hot-carrier effects in LDMOS, and suggestions have been made to mitigate such effects [4][5][6]. These attempts represent modest improvements in thermal management, but the devices are still likely to exhibit thermal problems.…”

Section: Introductionmentioning

confidence: 99%

Simulation of nonequilibrium thermal effects in power LDMOS transistors

Raman

Walker

Fisher

2003

Solid-State Electronics

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The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtained using a common electronic solution and three different heating models (Joule heating, electron/lattice scattering, phonon scattering). The results indicate that, under similar operating conditions, nonequilibrium behavior is more significant in the case of full SOI devices, where the extent of nonequilibrium is estimated to be twice that of the partial SOI device and four times that of the bulk device. Time development of acoustic phonon and lattice temperatures in the electrically active region indicates that nonequilibrium effects are significant for times less than 10 ns.

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“…2, there are three electric field peaks in device, adjunction region between channel and drift region (location 0), the channel side of STI region (location 1) and the drain side of STI region (location 2). They will possibly induce HCI effect [3][4][5] and get carriers injected into oxide, introducing normal electric field hence affect carrier transportation and electric field distribution in the device. Such effects of oxide charge are reproduced by interface charge.…”

Section: Device Structurementioning

confidence: 99%