2008
DOI: 10.1109/led.2008.2000610
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Effect of Drift-Region Concentration on Hot-Carrier-Induced $R_{\rm on}$ Degradation in nLDMOS Transistors

Abstract: In this letter, hot-carrier-induced on-resistance (R on ) degradation in lateral DMOS transistors with different n-type drift-drain (NDD) region concentration is investigated. Increasing NDD concentration results in greater bulk (I b ) and gate currents (I g ), but R on degradation is improved. Technology computer-aided design simulations reveal that high NDD concentration increases impact-ionization rate in accumulation (related to I b increase) and channel regions (related to I g increase) but reduces impact… Show more

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Cited by 23 publications
(7 citation statements)
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“…This can be understood from pairs/(cm 3 *s), which is higher than that of LNWD 1*10 22 pairs/(cm 3 *s). This is because the higher doping concentration in the NWD region of ONWD induces higher electric field and J E near this II peak, thereby increase the II generation rate [46,47]. This is also verified by the I SUB measurements as shown in Fig 42 where ONWD has higher I SUB , implying that it has higher II generation rate.…”
Section: Attention: the Singapore Copyright Act Applies To The Use Ofsupporting
confidence: 54%
“…This can be understood from pairs/(cm 3 *s), which is higher than that of LNWD 1*10 22 pairs/(cm 3 *s). This is because the higher doping concentration in the NWD region of ONWD induces higher electric field and J E near this II peak, thereby increase the II generation rate [46,47]. This is also verified by the I SUB measurements as shown in Fig 42 where ONWD has higher I SUB , implying that it has higher II generation rate.…”
Section: Attention: the Singapore Copyright Act Applies To The Use Ofsupporting
confidence: 54%
“…The first I sub peak occurs at V gs ¼ 4 V, this is similar to the behavior in conventional metal-oxide-semiconductor field- effect transistors (MOSFETs). When V gs > 8 V, I sub rises again because of the Kirk effect, 7,16) and the second I sub peak occurs at V gs ¼ 12 V. When the devices are stressed under V ds ¼ 40 V with various V gs (2.5, 4, 8, and 12 V), the device stressed under V gs ¼ 12 V degrades the most. As a result, the following analysis is focused on the device stressed under V gs ¼ 12 V. Figure 3 shows linear-region I d (measured at V ds ¼ 0:1 V) vs measured V gs before and after stress for the device stressed under V ds ¼ 40 V and V gs ¼ 12 V for 3000 s. A slight increase in I d is found when the device is stressed for 1 s, while I d decreases when the device is stressed for 3000 s. Such a phenomenon can be further recognized in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…Because LDMOS devices are usually operated under high drain voltage and high temperature conditions, such as in automotive applications, the stress-induced degradation becomes a major reliability issue in LDMOS transistors. [6][7][8][9][10][11] Most of reliability studied about STI-based LDMOS are focused on hot-carrier degradation, thus short of reliability information on high temperature stress degradation, especially for high temperature reverse bias (HTRB) stress mode, which is one of the most importance reliability issue in high voltage devices. 13) Moreover, the characterization technique and reliability degradation mechanism of LDMOSFETs differ substantially from standard CMOS devices due to the complex device architecture.…”
Section: Introductionmentioning
confidence: 99%
“…13) Moreover, the characterization technique and reliability degradation mechanism of LDMOSFETs differ substantially from standard CMOS devices due to the complex device architecture. [6][7][8][9][10][11] There is growing evidence that the presence of bulk and interface states is responsible for the degradation of the intrinsic electronic performance of LDMOSFETs. [12][13][14] Up to now, besides the traditional I d -V g method, some other characterization techniques, i.e., the charge-pumping (CP), 15) multiple level charge-pumping (MLCP) technique, 16,17) low-frequency 1/f noise, [18][19][20] and multi-region direct-current current-voltage (MR-DCIV) 21,22) technique have been developed for characterizing interface states in LDMOSFETs.…”
Section: Introductionmentioning
confidence: 99%