Hybrid Approach to Faster Functional Verification with Full Visibility

Chuang, Chin-Lung; Cheng, Wei-Hsiang; Liu, C.-N.J.; Lu, Deng-Fong

doi:10.1109/mdt.2007.46

Cited by 17 publications

(9 citation statements)

References 4 publications

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“…For larger and more complex systems, simulators can hardly be employed, due to the huge requirements in terms of computational power and time. Emulation represents a viable improvement, enabling faster system behavior replication, but often with reduced system observability [1][2][3][4][5][6]. Commercial platforms are available for several architectures, based on simulators, emulators and/or programmable hardware, each one offering a specific set of features and possibly introducing a significant setup cost in the design flow.…”

Section: Discussionmentioning

confidence: 99%

A Low-Cost Emulation System for Fast Co-verification and Debug

Lagos

Grosso

Sterpone

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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A flexible system for SoC co-verification is proposed, built around an Infrastructure Microprocessor (IM), providing improved controllability and observability in a fast self-contained FPGA-based emulation environment. In addition, software debug is supported by enabling observation of critical signals, breakpoint setting and stepby-step execution with total memory accessibility. Experimental results in an industrial case study confirm the effectiveness of the approach for validating and debugging hardware and software. SUMMARYGuaranteeing the implementation correctness of today's integrated systems, which may include microprocessor and logic cores as well as several software layers, is becoming a daunting task. Finding design or implementation bugs requires the activation of the devices in functional mode while feeding them with input data and control signals, replicating complex and possible long operating sequences, and observing critical signals. Single hardware modules and small low-level code segments can be efficiently reproduced and analyzed in simulation, employing testbenches, or verified through formal techniques. For larger and more complex systems, simulators can hardly be employed, due to the huge requirements in terms of computational power and time. Emulation represents a viable improvement, enabling faster system behavior replication, but often with reduced system observability [1-6]. Commercial platforms are available for several architectures, based on simulators, emulators and/or programmable hardware, each one offering a specific set of features and possibly introducing a significant setup cost in the design flow.A co-verification and debug system is here proposed (Fig.1), based on full FPGA emulation of the circuit design and on a dedicated microprocessor-based interface. The emulation environment is self-contained and runs at high speed. Complete controllability on the inspected device is achieved, including I/O signals, clocks and memories, so as to perform hardware validation/verification and supporting software debug, while the development of tests relies on writing high-level code routines. In addition, the adaption to different circuits takes minimal redesign effort, making the system particularly suitable to follow the different development steps of a new complex device. To enable effective use, a supporting software environment was developed, ranging from HDL simulators, ad-hoc flow management tools, up to high-level system models. The platform presented herein extends the capabilities of our previous work [7] by providing additional control and observation features in order to interact more deeply with the emulated system. Also, we demonstrate the possibility of adding purpose-specific verification support modules to the emulation system in order to perform specific tasks, such as bus protocol conversions or noise injection.

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Section: Discussionmentioning

confidence: 99%

A Low-Cost Emulation System for Fast Co-verification and Debug

Lagos

Grosso

Sterpone

et al. 2011

2011 Sixteenth IEEE European Test Symposium

View full text Add to dashboard Cite

show abstract

“…However, initialization of the DUT in simulator has been stated as an overhead and scalability problem has not been addressed. In [4,5], a functional debugging capability with FPGAs and simulators has been described. The internal behavior of an FPGA is recorded and the interesting period in time is replayed in a software simulator for debugging.…”

Section: Previous Workmentioning

confidence: 99%

“…Hybrid systems harnessing the advantages of both simulation and emulation have been widely used for fast functional verification and debug [3,4,5,6,7,8]. Long test sequences are run on emulator and upon error detection, the DUT is loaded on a simulator for debugging, with the help of checkpoints or design snapshots saved during emulation.…”

Section: Introductionmentioning

confidence: 99%

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Banerjee¹,

Gupta²

2012

Proceedings of the International Conference on Computer-Aided Design

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Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents a completely scalable hybrid verification and debug system based on dynamically reconfigurable co-simulation. Unlike existing systems, it allows one or more component logic blocks of a SoC to run on simulator for debugging while rest of the design still runs on emulator. The full design under test (DUT) is run on emulator at near hardware speed for long test sequences, and on error detection one or more logic blocks are transparently switched over to simulation for debugging, initializing the system as a piecewise cosimulator. Logic blocks can be flexibly relocated between simulator and emulator dynamically, without going through time consuming design recompilation phase, allowing designers to quickly debug functional issues. Application of the system to verification of real complex designs shows the effectiveness of our approach.

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“…Another FPGA debug method known as simulation reconstruction was developed long time ago and has been 978-1-4244-8223-8/10/$26.00 ©2010 IEEE evolved recently [9]. A snapshot method for FPGA debug is proposed to record the behavior of FPGA and replay it in HDL simulator.…”

Section: Related Workmentioning

confidence: 99%

A run-time RTL debugging methodology for FPGA-based co-simulation

Cheng

Ruan

Liao

et al. 2010

2010 International Conference on Communications, Circuits and Systems (ICCCAS)

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Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. FPGA-based cosimulation seems to draw a balance, but Design Under Test (OUT) still resides in FPGA and remains hard for debugging. So a run-time RTL debugging methodology for FPGA-assisted verification system is presented. This method provides internal nodes probing on an event-driven cosimulation platform and achieves full observability for OUT. The debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of OUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI-extended bus, instead of inserting extra scan-chain logic, so the overhead for area is reduced. Our experiment shows that, compared with a similar method in (13], the area overhead for debug logic is reduced by 30-50% and compile time is shortened by 40-70%.

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Hybrid Approach to Faster Functional Verification with Full Visibility

Cited by 17 publications

References 4 publications

A Low-Cost Emulation System for Fast Co-verification and Debug

A Low-Cost Emulation System for Fast Co-verification and Debug

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

A run-time RTL debugging methodology for FPGA-based co-simulation

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