Hybrid Nanodielectrics for Low‐Voltage Organic Electronics

Luzio, Alessandro; Ferré, F. García; Fonzo, Fabio Di; Caironi, Mario

doi:10.1002/adfm.201302428

Cited by 43 publications

(34 citation statements)

References 69 publications

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“…P(NDI2OD-T2) was spin-coated yielding 40-50 nm thick fi lms. We adopted a double layer dielectric stack, comprised of a 350 nm thick poly (methyl methacrylate) (PMMA) fi lm and of a 400 nm thick alumina layer deposited by pulsed laser deposition (PLD), [ 41 ] since alumina is very effective in suppressing gate leakage currents without compromising the overall gate capacitance thanks to its high dielectric constant. The leakage current was as low as 1 nA cm −2 (Figure 2 b).…”

Section: Resultsmentioning

confidence: 99%

Injection Length in Staggered Organic Thin Film Transistors: Assessment and Implications for Device Downscaling

Natali

Chen

Maddalena

et al. 2016

Adv Elect Materials

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of organic semiconductors show carrier mobility in excess of 5 cm 2 V −1 s −1 when employed as active materials in long (>10 μm) channel organic thin fi lm transistors (OTFT). [2][3][4][5][6][7][8][9][10][11][12] Therefore by scaling the channel length down to 10-1 μm, in principle OTFTs should be able to operate at relatively high (1-10 MHz) frequencies at reasonable (<10 V) applied voltages. [ 13 ] In practice, apart from some reports, [13][14][15][16][17][18][19][20][21][22] this is often not easy to achieve because of injection issues: [ 23,24 ] contact resistances tend to become dominant over the channel resistance in short channel transistors reducing the expected improvement of device performances. [ 25 ] This situation is severely limiting the range of applications for OTFTs. [ 26 ] Indeed contact resistances arise from contact/semiconductor interface properties hence they are not expected to scale with the transistor channel length. To address this issue not only suitable modifi cations of the contact/semiconductor interface aimed at enhancing the contact injecting properties have to be implemented, [ 27 ] but also the device topology has to be considered. Staggered OTFTs, where the contacts and the transistor channel do not lie in the same plane, are usually characterized by lower contact resistances than coplanar ones: [ 28 ] while in these latter the injection area is limited by the accumulated channel depth (few nanometers), in the former the overlap between gate and source/drain contacts (many micrometers or even tens of micrometers) can be exploited, as shown in Figure 1 . The gate/contact overlapping length has to be suitably engineered: on the one hand it should be large enough to accommodate the injected current and to minimize contact resistances; but on the other hand it should not be too large because overlapping areas not effectively involved in injection solely result in additional parasitic capacitances that deteriorate the device speed. [ 13,29 ] It is therefore important to quantify the injection length, which is the length over which sizeable carrier injection occurs. [ 30,31 ] Despite the large number of studies on contact effects in OTFTs, [ 24,32 ] few of them discuss the effect of the gate to contact overlap: Xu et al. found a relationship between the optimal contact length and the semiconductor thickness in staggered OTFT. [ 33 ] Park et al. found that threshold voltage, fi eld effect mobility and contact resistances are affected by the contact length in staggered OTFT; [ 34 ] Wang et al. simulated the effect of contact length scaling. [ 35 ] Ante et al. studied the effect of contact In staggered thin fi lm transistors, the injection length is the fraction of the gate to contact overlap that is effectively involved in current injection. Its assessment is important to properly downscale device dimensions. In fact, in order to increase transistor operation speed, the whole device footprint should be downscaled, which means both the gate to contact overlap and the channel length, as ...

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Section: Resultsmentioning

confidence: 99%

Injection Length in Staggered Organic Thin Film Transistors: Assessment and Implications for Device Downscaling

Natali

Chen

Maddalena

et al. 2016

Adv Elect Materials

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“…1 Lowvoltage operation of OTFTs has been demonstrated for devices fabricated via numerous techniques including, roll-to-roll (R2R) printing, 2 thermal evaporation, 3,4 vapour-phase deposition, 5,6 and spin-coating methods, [7][8][9] as well as through the use of self-assembled monolayer nano-dielectrics, 10-12 electrolyte dielectrics, [13][14][15] and ultra-thin polymer dielectrics. 3,7,8 However, with the exception of R2R processing, none of these fabrication techniques are suitable for high-throughput manufacturing, which is critical for the development of ubiquitous, disposable electronics based on OTFTs.…”

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confidence: 99%

Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

Hunter

Ward

Payne

et al. 2015

Applied Physics Letters

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Organic thin-film electronics have long been considered an enticing candidate in achieving high-throughput manufacturing of low-power ubiquitous electronics. However, to achieve this goal, more work is required to reduce operating voltages and develop suitable mass-manufacture techniques. Here, we demonstrate low-voltage spray-cast organic thin-film transistors based on a semiconductor blend of 2,8-difluoro- 5,11-bis (triethylsilylethynyl) anthradithiophene and poly(triarylamine). Both semiconductor and dielectric films are deposited via successive spray deposition in ambient conditions (air with 40%–60% relative humidity) without any special precautions. Despite the simplicity of the deposition method, p-channel transistors with hole mobilities of >1 cm2/Vs are realized at −4 V operation, and unipolar inverters operating at −6 V are demonstrated.

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“…[ 1 ] Recent progress has provided polymer Solution-processed polymer-based logic circuits are typically associated with high operating voltage and slow switching speeds. [ 7,8 ] A strategy to decrease PFET operating voltages is to increase the area-normalized gate capacitance ( C ). Suitable device engineering, controllable dielectric parameters, and interface energetics enable PFET operation at ±1 V, fi eld-effect mobility ( µ FET ) > 2.0 cm 2 V −1 s −1 , subthreshold swing ≈100 mV dec −1 , and switching response ≈150 ns.…”

Section: Introductionmentioning

confidence: 99%

“…[ 6,7 ] However, typical devices require high temperature fabrication ( T > 400 °C) and are not scalable to arbitrary numbers of layers, [ 6,7,19 ] thus limiting the capacitance, leakage, and scaling properties of the dielectric structure. [ 6,7 ] However, typical devices require high temperature fabrication ( T > 400 °C) and are not scalable to arbitrary numbers of layers, [ 6,7,19 ] thus limiting the capacitance, leakage, and scaling properties of the dielectric structure.…”

Section: Introductionmentioning

confidence: 99%

“…[ 6,7 ] However, typical devices require high temperature fabrication ( T > 400 °C) and are not scalable to arbitrary numbers of layers, [ 6,7,19 ] thus limiting the capacitance, leakage, and scaling properties of the dielectric structure. [ 5,14 ] Furthermore, SANDs enhance the static response parameters in organic semiconductor, [ 7 ] carbon nanotube, [ 22 ] graphene, [ 23 ] and amorphous oxide FETs. [ 5,14 ] Furthermore, SANDs enhance the static response parameters in organic semiconductor, [ 7 ] carbon nanotube, [ 22 ] graphene, [ 23 ] and amorphous oxide FETs.…”

Section: Introductionmentioning

confidence: 99%

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Self‐Assembled Nanodielectrics for High‐Speed, Low‐Voltage Solution‐Processed Polymer Logic Circuits

Senanayak

Sangwan

McMorrow

et al. 2015

Adv Elect Materials

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Solution‐processed polymer‐based logic circuits are typically associated with high operating voltage and slow switching speeds. Here, polymer field‐effect transistors (PFETs) fabricated on hybrid self‐assembled nanodielectric (SAND) structures are reported, the latter consisting of alternating organic–inorganic layers exhibiting low leakage current (≈10−9 A cm−2) and high capacitance (≈0.8 μF cm−2). Suitable device engineering, controllable dielectric parameters, and interface energetics enable PFET operation at ±1 V, field‐effect mobility (μ FET) > 2.0 cm2 V−1 s−1, subthreshold swing ≈100 mV dec−1, and switching response ≈150 ns. These performance parameters are orders of magnitude higher than similar devices fabricated from other polymer dielectrics. Inverter and NAND logic circuits fabricated from these SAND‐based PFETs possess voltage gain up to 38 and maximum‐frequency bandwidth of 2 MHz. A systematic study comparing different classes of dielectric and semiconducting material attributes the enhanced performance to improved relaxation dynamics of the SAND layer and tunable chemically functionalized interfaces.

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Hybrid Nanodielectrics for Low‐Voltage Organic Electronics

Cited by 43 publications

References 69 publications

Injection Length in Staggered Organic Thin Film Transistors: Assessment and Implications for Device Downscaling

Injection Length in Staggered Organic Thin Film Transistors: Assessment and Implications for Device Downscaling

Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

Self‐Assembled Nanodielectrics for High‐Speed, Low‐Voltage Solution‐Processed Polymer Logic Circuits

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