Hyper-Dimensional Computing Challenges and Opportunities for AI Applications

Hassan, Eman; Halawani, Yasmin; Mohammad, Baker; Saleh, Hani

doi:10.1109/access.2021.3059762

Cited by 39 publications

(28 citation statements)

References 65 publications

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“…• Store all encoded patterns in the associative memory (AM). MNIST for supervised classification using orthogonal encoding using HDC paradigm has been carried out in 23 using MATLAB. And in this work, the inference phase is considered only so the IM and the AM modules are established.…”

Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

“…The work proposed in this paper focuses on the physical implementation of XNOR-based RRAM-CAM for HDC classification. Nonetheless, in our paper 23 , simulations for both encoding/training and testing/inference phases for MNIST data-set were carried out. The effect of training data-set size, partial training, and chosen dimension d on the classification accuracy was studied.…”

Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

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RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

Halawani

Kilani

Hassan

et al. 2021

Sci Rep

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Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

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Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

Halawani

Kilani

Hassan

et al. 2021

Sci Rep

Self Cite

View full text Add to dashboard Cite

show abstract

“…HD computing is inspired by the dimensionality expansion of information processing happening in the human nervous system. The further we go from the sensors, the more abstract levels of information representation are available 18,19 . Also, HDC can perform approximate computations instead of exact due to the neuron's holographic representation where the bit value is independent of its position, unlike conventional computing 18 .…”

Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

“…A typical binary image data set goes through the following steps during the encoding/ training phase for supervised classification using orthogonal encoding as in 25 . The functionality of this module was verified in MATLAB 19 .…”

Section: Hyperdimensional Computing Architecture Demonstratormentioning

confidence: 99%

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Halawani

Kilani

Hassan

et al. 2021

Preprint

Self Cite

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Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

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“…There is no previous article that would account for all currently known applications, though there are recent works overviewing either a particular application area (as in [344], where the focus was on biomedical signals), or certain application types (as in [110,131], where solving ✓ means that the article overviewed the area rather comprehensively, ✗ means that the area was not covered at all while ± indicates that the article partially addressed a particular topic, but either new results were reported since then or not all related work was covered.…”

Section: Introductionmentioning

confidence: 99%

A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part II: Applications, Cognitive Models, and Challenges

et al. 2023

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This is Part II of the two-part comprehensive survey devoted to a computing framework most commonly known under the names Hyperdimensional Computing and Vector Symbolic Architectures (HDC/VSA). Both names refer to a family of computational models that use high-dimensional distributed representations and rely on the algebraic properties of their key operations to incorporate the advantages of structured symbolic representations and vector distributed representations. Holographic Reduced Representations [322, 327] is an influential HDC/VSA model that is well-known in the machine learning domain and often used to refer to the whole family. However, for the sake of consistency, we use HDC/VSA to refer to the field. Part I of this survey [223] covered foundational aspects of the field, such as the historical context leading to the development of HDC/VSA, key elements of any HDC/VSA model, known HDC/VSA models, and the transformation of input data of various types into high-dimensional vectors suitable for HDC/VSA. This second part surveys existing applications, the role of HDC/VSA in cognitive computing and architectures, as well as directions for future work. Most of the applications lie within the Machine Learning/Artificial Intelligence domain, however, we also cover other applications to provide a complete picture. The survey is written to be useful for both newcomers and practitioners.

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Hyper-Dimensional Computing Challenges and Opportunities for AI Applications

Cited by 39 publications

References 65 publications

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part II: Applications, Cognitive Models, and Challenges

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