J _SWof 5.5 MA/cm² and RA of 5.2-Ω · μm² STT-MRAM Technology for LLC Application

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

“…Larger on-chip buffer memory is needed to minimize DRAM accesses, and it can improve the energy efficiency and speed of the accelerator. However, conventional Static Random-Access Memory (SRAM) based solutions suffer from area constraints and leakage power at advanced technology nodes [6], [7], which is a major concern for the energyconstraint IoT domain. STT-MRAM has the potential to replace SRAM as the global buffer in high-performance AI accelerators that require large on-chip memory [3], [8].…”

“…The emerging resistive RAM (RRAM) and Phase Change (PCM) based cross-point memory suffers from endurance, reliability and variability problems [7], [11]. Among all the emerging embedded memory technologies, STT-MRAM is one of the most promising due to its high energy efficiency, write endurance (e.g., more than 1 million cycles), high cell density, high-temperature data retention capability, operating voltage comparable with CMOS logic, and immunity to soft errors [6], [7], [12]- [16]. Moreover, STT-MRAM is higly compatible with CMOS and requires only 2 to 6 extra masks in the backend-of-the-line (BEOL) process [6], [13].…”

“…Among all the emerging embedded memory technologies, STT-MRAM is one of the most promising due to its high energy efficiency, write endurance (e.g., more than 1 million cycles), high cell density, high-temperature data retention capability, operating voltage comparable with CMOS logic, and immunity to soft errors [6], [7], [12]- [16]. Moreover, STT-MRAM is higly compatible with CMOS and requires only 2 to 6 extra masks in the backend-of-the-line (BEOL) process [6], [13]. Because of the leakage power issue, beyond a certain memory size, embedded MRAM becomes more energy efficient compared to SRAM [6].…”

“…Moreover, STT-MRAM is higly compatible with CMOS and requires only 2 to 6 extra masks in the backend-of-the-line (BEOL) process [6], [13]. Because of the leakage power issue, beyond a certain memory size, embedded MRAM becomes more energy efficient compared to SRAM [6].…”

“…Because of compact size ( 6F 2 of STT-MRAM vs. 100F 2 of SRAM [17], [18]), STT-MRAM has the potential to outperform conventional SRAM as the on-chip memory in accelerators. At iso-memory capacities, the MRAM module occupies much lower area compared to SRAM [6]. Additionally, for power constraint mobile/edge/IoT applications, STT-MRAM based AI accelerators can significantly minimize static power compared to SRAMs.…”