ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking

Glokler, T.; Bitterlich, S.; Meyr, H.

doi:10.1109/asic.2000.880684

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…The structure of the generated encoding is very similar to the original design.Almost the same applies for the findings for the PowerPC model. The ICore [18] is a typical representative of an highly specialized ASIP architecture. It has been designed for acquisition and tracking tasks within a DVB-T receiver.…”

Section: Resultsmentioning

confidence: 99%

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Nohl¹,

Greive²,

Braun³

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodology is based on successive processor model refinement combined with simulation and profiling. Previous approaches require the tedious manual specification of binary instruction opcodes even at very early design stages due to the need to generate profiling tools. The proposed automatic technique eliminates this bottleneck in ASIP design. It is well adapted to the hierarchical processor modeling style of contemporary architecture description languages. Experimental evaluation for several real-life processor architectures confirms the practical applicability of the presented encoding techniques. Moreover, the results indicate that very compact instruction encoding schemes are generated that compete very well with hand-optimized encodings.

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Section: Resultsmentioning

confidence: 99%

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Nohl¹,

Greive²,

Braun³

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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show abstract

“…In this way, they achieve a good compromise between flexibility and efficiency. Examples of this kind are ICORE [251], SODA [281], a channel decoder architecture for third-generation mobile wireless terminals [78], and an ASIP for Internet Protocol Security (IPSec) encryption [109].…”

Section: Retargetable Compilersmentioning

confidence: 99%

C Compilers for ASIPs

Hohenauer

Leupers

2010

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“…An assembly-level compatible 16-bit architecture of M68HC11 is developed for this experiment. The ICORE [20] architecture is dedicated for Terrestrial Digital Video Broadcast (DVB-T) decoding. It is based on a Harvard architecture with a 4-stage pipeline implementing a set of general purpose arithmetic instructions as well as specialized trigonometric operations.…”

Section: Resultsmentioning

confidence: 99%

Optimization Techniques for ADL-Driven RTL Processor Synthesis

Schliebusch

Chattopadhyay

Witte

et al.

16th IEEE International Workshop on Rapid System Prototyping (RSP'05)

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Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space exploration in a higher level of abstraction. This increase in the abstraction level traditionally comes at the cost of low performance of the final Application Specific Instructionset Processor (ASIP) implementation, which is generated automatically from the ADL. There is a pressing need of novel optimization techniques for high level synthesis from ADLs, to compensate for this loss of performance. Two important aspects of these optimizations are the efficient usage of available structural information in the high level architecture descriptions and prudent pruning of overhead, introduced by mapping from ADL to Register Transfer Level (RTL). In this paper, we present two high level optimization techniques, path sharing and decision minimization. These optimization techniques are shown to be of lower complexity, by at least two orders, compared to similar optimization during gate-level synthesis. The optimizations are tested for a RISC architecture, a VLIW architecture and two industrial embedded processors, Motorola M68HC11 and Infineon ICORE. The results indicate a significant improvement in overall performance.

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ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking

Cited by 11 publications

References 6 publications

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Instruction encoding synthesis for architecture exploration using hierarchical processor models

C Compilers for ASIPs

Optimization Techniques for ADL-Driven RTL Processor Synthesis

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