Identifying the potential of near data processing for apache spark

Awan, Ahsan Javed; Ohara, Moriyoshi; Ayguadé, Eduard; Ishizaki, Kazuaki; Brorsson, Mats; Vlassov, Vladimir

doi:10.1145/3132402.3132427

Cited by 10 publications

(8 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Traditionally workload characterization is done using hardware performance counters present on our current microprocessors. Awan et al [50] use hardware performance counters to characterize the scale-out big data processing workloads into CPU-bound, memory-bound, and I/O-bound applications and propose programmable logic near DRAM and NVRAM. However, the use of hardware performance counters is limited by the impact of micro-architecture features like cache size, issue width etc [51].…”

Section: Microarchitecture-dependent Workload Characterizationmentioning

confidence: 99%

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Singh¹,

Chelini²,

Corda³

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

View full text Add to dashboard Cite

DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

show abstract

Section: Microarchitecture-dependent Workload Characterizationmentioning

confidence: 99%

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Singh¹,

Chelini²,

Corda³

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

View full text Add to dashboard Cite

show abstract

“…Unfortunately, the integration of a profiler (such as Perf or Pin) in a compiler or run-time system is still a challenging task [68] due to its dynamic nature. Therefore, current solutions rely on commercial profiling tools, such as Intel VTune [70], to detect the offloading kernels [30], [67], [69]. Additionally, some works [30], [38], [56] use the bandwidth saving as an offloading metric.…”

Section: Discussionmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

Self Cite

View full text Add to dashboard Cite

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

show abstract

“…NDPproposals have explored many memory architectures. In the literature, SRAM-based NDP proposals mostly aim to insert logic capabilities to the host's cache memories or to the host's memory controllers [17,19,20,21,22,23,24,58,59,103,106]. This work modify the cache hierarchy trying to avoid moving data from the main memory and cache memories to the host's core.…”

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

View full text Add to dashboard Cite

One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption. In this context, Near-Data Processing (NDP) proposals have started to gain acceptance as an accelerator device. Such proposals alleviate the memory bottleneck by moving instructions to data whereabouts. The first proposals date back to the 1990s, but it was only in the 2010s that we could observe an increase in papers addressing NDP. It occurred together with the appearance of 3D-stacked chips with logic and memory stacked layers. This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures. We also introduce a new taxonomy to classify such architectural proposals according to their data distance.

show abstract

Identifying the potential of near data processing for apache spark

Cited by 10 publications

References 28 publications

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Near-memory computing: Past, present, and future

Survey on Near-Data Processing: Applications and Architectures

Contact Info

Product

Resources

About