IGZO TFT gate driver circuit with large threshold voltage margin

Kim, Jin-Ho; Oh, Jongsu; Park, KeeChan; Kim, Yong−Sang

doi:10.1016/j.displa.2018.03.003

Cited by 28 publications

(27 citation statements)

References 16 publications

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“…3 (c) and (d) shows the very good VOUT waveform of the proposed circuit. The proposed gate driver was designed with the AC driven pull-down TFT based on the circuit design concept of the improved negative V th limit for circuit operation using depletion mode a-IGZO TFT in our previous work [15]. The negative V th limit for circuit operation of the proposed circuit was slightly higher than that of the proposed circuit with DC driven in our previous work [15].…”

Section: Resultsmentioning

confidence: 93%

“…In this paper, we propose a gate driver structure with an AC driven pull-down TFT in order to gain high stability, and the DC leakage current path was avoided in the gate driver in order to ensure low power consumption. The proposed gate driver is designed with an AC driven pull-down TFT that is based on the circuit design concept of the improved negative V th limit for circuit operation and low power using the depletion mode a-IGZO TFT in our previous works [14][15]. The driving characteristics, negative V th limit for circuit operation, and power consumptions of the proposed gate driver circuit were verified using both circuit simulations and circuit analysis.…”

Section: Introductionmentioning

confidence: 99%

“…Because the proposed circuit was driven by a capacitor for the AC driven P node, the proposed circuit is designed without the DC leakage path. Figure 2 shows the measured and simulated transfer characteristics of the depletion a-IGZO TFT [15]. Assuming a video graphics HD (1366 × 768) display panel, we attached a 4kΩ resistor and a 100pF capacitor to each output node to emulate the gate line load for simulation.…”

Section: Introductionmentioning

confidence: 99%

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P‐46: Gate Driver Circuit with AC Driven Pull‐down TFT for Depletion Mode a‐IGZO TFTs

Kim

Park

et al. 2018

Symp Digest of Tech Papers

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This paper proposes a new gate driver using depletion mode a-IGZO thin film transistors (TFTs). We propose the gate driver structure with an AC driven pull-down TFT in order to gain high stability, to decrease the threshold voltage (V th ) shift of the pull-down TFT, and a gate driver without a DC leakage current path in order to gain low-power consumption. The proposed gate driver is designed with a capacitor coupling driving circuit for an AC driven pull-down TFT that is based on the circuit design concept of the improved negative V th limit for circuit operation and low-power using the depletion mode a-IGZO TFT, as presented in our reported paper. The proposed gate driver circuit with the AC driven pull-down TFT maintain the almost same normalized value at -1~3V of V th range when compared to the results of circuit with the DC driven pull-down TFT in the published paper by our group. However, the proposed circuit has the lower normalized value at -5~-3V of V th range when compared to the result of circuit in our reported paper. The proposed circuit can maintain the power consumption within 3.65 times of the normal value if -5V of the V th of the a-IGZO TFTs.

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Section: Resultsmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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P‐46: Gate Driver Circuit with AC Driven Pull‐down TFT for Depletion Mode a‐IGZO TFTs

Kim

Park

et al. 2018

Symp Digest of Tech Papers

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“…Figure shows comparison of the Q node and V OUT waveform characteristics for the fifth stage based on the QB node driving method. The results show that the Q node voltage in the precharge period with AC‐driven and DC‐driven methods was +27.5 and +26.5 V, respectively, despite the same threshold voltage of +0.5 V. In addition, the Q node bootstrapping voltages were +56.7 and +54.1 V, respectively, because pull‐down unit (T3) for Q node was not completely turned off due to VDD voltage through T4 . Consequently, the V OUT output characteristic was decreased by Q node voltage degradation.…”

Section: Resultsmentioning

confidence: 98%

“…The results show that the Q node voltage in the precharge period with AC-driven and DC-driven methods was +27.5 and +26.5 V, respectively, despite the same threshold voltage of +0.5 V. In addition, the Q node bootstrapping voltages were +56.7 and +54.1 V, respectively, because pull-down unit (T3) for Q node was not completely turned off due to VDD voltage through T4. 18 Consequently, the V OUT output characteristic was decreased by Q node voltage degradation. Compared with the AC-driven method, the DC-driven method has a larger rising time and falling time of 0.1 μs.…”

Section: Resultsmentioning

confidence: 99%

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

Jung

Lee

et al. 2019

J Soc Info Display

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In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (VGS) value for pull‐down units. The results showed all the VOUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable VOUT voltage when the threshold voltage for all TFTs was changed from −6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved VOUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.

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Influence of UV/Ozone Treatment on Threshold Voltage Modulation in Sol–Gel IGZO Thin‐Film Transistors

Kim

Lee

Kwak

et al. 2022

Adv Materials Inter

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high-throughput production [9][10][11][12] with good electrical/optical performances. [3][4][5] By implementing them as active semiconductor layers in thin-film transistors (TFTs), [1][2][3] transparent displays, [6,8,13] optoelectrical sensors, [1,5,14] neuromorphic devices, [15][16][17][18] and functional devices on flexible substrates [1,6,7] have been extensively demonstrated, implicating feasible practical applications for future electronic devices.

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IGZO TFT gate driver circuit with large threshold voltage margin

Cited by 28 publications

References 16 publications

P‐46: Gate Driver Circuit with AC Driven Pull‐down TFT for Depletion Mode a‐IGZO TFTs

P‐46: Gate Driver Circuit with AC Driven Pull‐down TFT for Depletion Mode a‐IGZO TFTs

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

Influence of UV/Ozone Treatment on Threshold Voltage Modulation in Sol–Gel IGZO Thin‐Film Transistors

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