III-V Compounds-on-Si: Heterostructure Fabrication, Application and Prospects

Abstract

While silicon and gallium arsenide are dominant materials in modern micro-and nanoelectronics, devices fabricated from them still use Si and GaAs substrates only separately. Integrating these materials on the large and cheep Si substrate has been the subject of enormous research efforts for the past three decades. This review attempts to systematize and generalize the current understanding of the fundamental physical mechanisms governing the epitaxial growth of GaAs and related III-V compounds on Si substrates. Different kinds of bonding as a very promising non-epitaxial method for III-V thin film integration on Si substrate are reviewed. Basic techniques available for improving the quality of such heterostructures are described, and recent advances in fabricating of device-quality III-V-on-Si heterostructures and corresponding devices are also presented.

Effect of bulk growth temperature on antiphase domain boundary annihilation rate in MOCVD-grown GaAs on Si(001)

“…Threading dislocation density can be reduced through the use of buffer layers to alleviate lattice strain [3][4][5][6]. GaAs is a good candidate for a buffer layer material because of its intermediate lattice constant between InGaAs/InAs and Si and so it is important to first obtain high-quality epitaxy of GaAs on Si.…”

GaAs/Ge/Si epitaxial substrates: Development and characteristics

“…Even though APB can now be dealt with through using Si substrates misoriented from the singular plane (001) to (110) by 4-6 • , the problem of reducing the threading dislocations density (TDD) in the GaAs layer proves to be a lot harder to overcome. [5][6][7][8] Due to a nearly 4% difference between the Si and GaAs lattice parameters, the TDD in the GaAs layer obtained through direct growth of GaAs on Si reaches the values of 10 9 -10 10 cm -2 . The difference in the thermal expansion coefficients of Si and GaAs also contributes to an increasing amount of dislocations and to the formation of cracks in the GaAs layer during cool down.…”

Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

“…Among III-V compound semiconductors, indium phosphide (InP) has attracted much interest for various applications including high speed optoelectronics for optical communications [1][2][3]. In order to satisfy the requirements to be used in InP-based optoelectronic devices as well as low power logic devices with high performance, the high quality epitaxial growth of InP on Si substrates is essentially necessary.…”