Effects of growth temperature on surface morphology of InP grown on patterned Si(0 0 1) substrates

Heteroepitaxy of III–V Zinc Blende Semiconductors on Nanopatterned Substrates

“…The trench masks can be fabricated (i) by oxidation of the Si substrate surface, lithography and reactive ion etching, or alternatively (ii) by using processes based on the established shallow trench isolation technology [32]. In particular, selective-area MOVPE growth of InP and GaAs on trench mask patterned Si(001) substrate has attracted great interest [25,[33][34][35][36][37][38][39][40][41][42][43]. Although the detailed defect reduction mechanism depends on the trench dimensions, on the shape of the trench bottom as well as on the heteroepitaxial growth sequence and conditions, the common characteristic (Reproduced from [30], with the permission of AIP Publishing.…”

“…Furthermore, it has been found that the surface morphology of InP layers deposited selectively in trenches critically depends on the MOVPE growth conditions, especially on temperature and pressure [36,38]. These parameters determine the precursor/adatom diffusivity and the heat transfer from the substrate to its surroundings, thus the growth rates of different facets.…”

“…Concerning the main growth step similar, but slightly different layer morphologies have been reported by different groups, depending on the structure of the patterned samples and the growth setup. By using phosphine as group-V precursor, a SiN x trench mask with rounded rectangular recess in the Si(001) substrate and GaP and InP low-temperature buffer layers Lee et al obtained wedge-shaped InP ridges bounded by {111} facets for a high growth temperature of 650°C (Figure 13(a)), whereas an atomically smooth InP(001) top surface resulted for 550°C (Figure 13(b)) [38]. In the latter case, GaP islands appeared on the Si sidewalls and in the course of continued InP deposition the lateral growth led to coalescence of opposing sidewall deposits before the recess was fully filled (Figure 13(c)).…”

“…On the one hand, buffer layers of a different material with a lattice parameter between those of the substrate and of the layer deposited on the trench bottom reduce the effective misfit. For the InP/Si system (i) Ge with a Ge/InP misfit of ∼4% [33,36] (Figure 12) and (ii) GaP avoiding the polarity mismatch at the InP/GaP interface [38] ( Figure 13) have been used as buffer materials. On the other hand, buffer layers of the layer material grown at low temperature help to achieve a relatively smooth layer surface, since at low temperature the reduced Ga adatom diffusivity promotes the formation of a large density of small nucleation islands, which rapidly coalesce.…”

Influence of Growth Temperature of the Nucleation Layer on the Growth of InP on Si (001)

“…Therefore, it is important to find out the optimal growth parameters for the InP nucleation layer. Many researches have been performed focused on the influences of growth temperatures, thickness, and flow ratio of V/III sources of Ge [22] or GaAs [23] nucleation layer on Si, or InP nucleation layer on GaAs [24,25] or Si [26] by MOCVD. The findings of the above studies indicate that these parameters have significant impact on the growth behaviors, such as surface morphology and crystal quality.…”