ILP based don't care bits filling technique for reducing capture power

Gulve, Rohini; Singh, Virendra

doi:10.1109/ewdts.2016.7807649

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…Gulve and Singh [30] presented a technique that uses ILP solver CPLEX to fill the don't care bits to reduce capture power during at-speed scan testing. It models the functionality of CUT as linear programming equations with optimization functions as minimized switching.…”

Section: Sat/ilp Solvermentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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Section: Sat/ilp Solvermentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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“…Minimization of the total weighted switching activity cropped up in the CUT is done through the formulation of ILP based zero-one linear problem (ZOLP) in [12]. ZOLP equations are formulated to minimize test mode switching activity by filling X bits of partially specified test patterns.…”

Section: X-filling For Capture Power Reductionmentioning

confidence: 99%

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Mitra¹,

Das²

2018

IJEECS

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Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don’t care bit(X) filling approaches are one of them in this fraternity. These don’t care(X) bit filling techniques have drawn the significant attention of industry and academia for its higher compatibility with existing design flow as neither modification of the CUT is required nor they need to rerun the time-consuming ATPG process. This paper presents an empirical survey of those X-bit filling techniques, applied to mitigate prime two types of dynamic power dissipation namely shift power and capture power, occurred during full scan testing.

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On Generation of Delay Test with Capture Power Safety

Gulve

Hage

2017

Communications in Computer and Information Science

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ILP based don't care bits filling technique for reducing capture power

Cited by 4 publications

References 9 publications

A survey of scan-capture power reduction techniques

A survey of scan-capture power reduction techniques

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

On Generation of Delay Test with Capture Power Safety

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