Image processing device for automotive vision systems

Matsumoto, Shoji; Otsuka, Yuji; Takenaga, Hiroshi; Kobayashi, Yoshiki; Monji, Tatsuhiko

doi:10.1109/ivs.2002.1187939

Cited by 12 publications

(6 citation statements)

References 8 publications

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“…9, subroutine (3) consists of the following six operations. (3-1) The shape of each white-line segment candidate is analyzed to obtain the length, width, and gravity center, (3-2, 3-3) Some of the candidates whose length or width is less than a threshold value are eliminated, (3-4) Some of the candidates whose position is far from the estimated white line position are eliminated, (3)(4)(5) After calculating the linearity of each white-line segment candidate, some of the candidates are eliminated if their linearity are less than a threshold value, After calculating each candidate angle made by the candidate axis and camera one, some candidates are eliminated if the angle is not allowed at that position when considering the road shape defined by the road traffic regulations.…”

Section: Verification Of White-line Segment Candidatesmentioning

confidence: 99%

“…†1 System IP Core Research Laboratories, NEC Corporation Various image recognition processors have been developed to satisfy these requirements. The Vchip (Vision/Video Chip), for example, implements basic operations for image recognition (such as an edge filter) as dedicated hardware 3) . By using the dedicated hardware, the Vchip can cost-effectively achieve high performance and low power consumption for pre-defined operations which are supported by the hardware, but it lacks flexibility to support diverse algorithms.…”

Section: Introductionmentioning

confidence: 99%

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Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

Nomoto

Kyo

Okazaki

2010

IPSJ Transactions on System LSI Design Methodology

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We have developed an "XC core" processor that achieves low cost, high performance, and low power consumption through the use of a highly parallel SIMD architecture (the SIMD mode), as well as achieves high flexibility by morphing into a MIMD architecture (MIMD mode). In this paper, we evaluate the effectiveness of the MIMD mode by using a white line detection algorithm for open roads. Our evaluation shows that the algorithm can be processed in real time (less than 33 ms) by using the MIMD mode to execute verification of white line segments, which is a part of the algorithm not suitable to be executed by the SIMD mode. We also show that the verification can be executed five times faster by using region of interest (ROI) transfer instructions to efficiently transfer the ROI of an image. Furthermore, we also measured the execution time in the MIMD mode with changing the number of processing units (PUs) used, from 2 to 4, 8, 16 and 32. The measured results show that the performance improvement rate slows down when using more than 16 PUs in the MIMD mode, mainly due to insufficient parallelism in the verification process. Overall, a 10.68 times speedup was achieved by using 32 PUs in the MIMD mode, compared with only using the SIMD mode.

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Section: Verification Of White-line Segment Candidatesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

Nomoto

Kyo

Okazaki

2010

IPSJ Transactions on System LSI Design Methodology

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show abstract

“…VCHIP [9] developed by Hitachi belongs to the first design approach, and has been adopted by NISSAN as the processing engine of an in-vehicle lane departure warning system in 2001. VCHIP consists of fundamental image processing dedicated circuits including several filtering functions, binarization and histogram processing, and is viewed as a hardware accelerator from the CPU.…”

Section: In-vehicle Vision Processor Design Approachesmentioning

confidence: 99%

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

Kyo

Okazaki

2008

J Sign Process Syst

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This paper presents IMAPCAR, a 100GOPS programmable highly parallel vision processor LSI consuming less than 2 W of power for in-vehicle vision tasks of driver assistance systems. First, requirements of vision processors for driver assistance systems as well as the characteristics of vision tasks for safety are summarized. Next, features in the design of IMAPCAR are described in detail, which comparing with a previous design, improved the performance for major vision tasks by a factor of 2.5 while reduced 50% of power. Design choices taken by other in-vehicle vision processors are also compared and analyzed. Finally, technology perspectives of future invehicle vision processors are discussed.

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“…The overall performance and energy use is often limited by the memory bandwidth [1], [2], [3], [4]. This problem has been addressed by multiresolution processing [5].…”

Section: Introductionmentioning

confidence: 99%

An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision

Zhu

Garg

Tsai

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-We introduce an energy efficient time-sharing pyramid pipeline architecture designed for multi-resolution image analysis in mobile computer vision. The time-sharing pipeline efficiently reduces the off-chip memory traffic by re-organizing the data storage and processing order of an image pyramid. We build a parameterized image pyramid hardware generator and successfully evaluate the overall pyramid design space. Our results demonstrate that the time-sharing pyramid pipeline achieves about 50% of hardware savings in terms of area and power consumption compared to the traditional linear pipeline implementation. We also implement the multi-resolution LucasKanade optical flow algorithm on the time-sharing pipeline, and demonstrate an order of magnitude savings in off-chip memory traffic and system energy consumption.

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Image processing device for automotive vision systems

Cited by 12 publications

References 8 publications

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision

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