Image Processing Using FPGAs

Bailey, Donald G.

doi:10.3390/jimaging5050053

Cited by 22 publications

(10 citation statements)

References 9 publications

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“…FPGAs can achieve both data parallelism and task parallelism within many image processing tasks. Unfortunately, simply putting a PC-based algorithm onto an FPGA usually gives disappointing results [34]. In addition, many image processing algorithms have been optimized for scalar processors.…”

Section: Fpga-based Image Processingmentioning

confidence: 99%

A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs

et al. 2022

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Developing Field Programmable Gate Array (FPGA)-based applications is typically a slow and multi-skilled task. Research in tools to support application development has gradually reached a higher level. This paper describes an approach which aims to further raise the level at which an application developer works in developing FPGA-based implementations of image and video processing applications. The starting concept is a system of streamed soft coprocessors. We present a set of soft coprocessors which implement some of the key abstractions of Image Algebra. Our soft coprocessors are designed for easy chaining, and allow users to describe their application as a dataflow graph. A prototype implementation of a development environment, called SCoPeS, is presented. An application can be modified even during execution without requiring re-synthesis. The paper concludes with performance and resource utilization results for different implementations of a sample algorithm. We conclude that the soft coprocessor approach has the potential to deliver better performance than the soft processor approach, and can improve programmability over dedicated HDL cores for domain-specific applications while achieving competitive real time performance and utilization.

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Section: Fpga-based Image Processingmentioning

confidence: 99%

A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs

et al. 2022

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“…A FPGA device is an array of logic blocks that can implement arbitrary parallel and pipelined operations, without the constraint of conventional multicores or GPGPUs [41,42]. These devices are typically suitable for exploiting the specific parallelism of low-level image processing algorithms [43][44][45]. There are many implementations of defect and edge detection algorithms in literature [43,44,46], but also in the case of FPGA the processing time of an image depends on the image size [44].…”

Section: Related Workmentioning

confidence: 99%

A pre‐processing technique to decrease inspection time in glass tube production lines

Vitis

Foglia

Prete

2021

IET Image Processing

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In case of glass tube for pharmaceutical applications, high-quality defect detection is made via inspection systems based on computer vision. The processing must guarantee realtime inspection and meet increasing rate and quality requirements. Defect detection in glass tubes is complicated by aspects that hamper the efficiency of state-of-the-art techniques. This paper presents a pre-processing algorithm which excludes portions of the image where defects are surely absent. The approach decreases the time for defect detection and classification phases (any detection algorithm can be applied), as they are applied only in high-probability candidate sub-image. We derive a methodology to get robust values of algorithm's parameters during production. The algorithm relies on detrended standard deviation and double threshold hysteresis, which solve issues related to the misalignment between illuminator and acquisition camera, and enable a robust detection despite rotation, vibration, and irregularities of tubes. We consider Canny, MAGDDA, and Niblack algorithms. The solution keeps the detection quality of such algorithms and reaches a 4.69× throughput gain. It represents a methodology to obtain defect detection in timeconstrained environments through a software-only approach, and can be exploited in parallel/accelerated solutions and in contexts where a linear camera is utilized on both flat and uneven surfaces.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…Classification algorithms such as k-means, k-nearest neighbours (kNN), and mean-shift have been implemented frequently on FPGAs [23]. Although GPUs already enjoyed widespread use in data centers, to allow parallel processing of the large amounts of data required by these tasks, it was the relative energy efficiency of FPGAs that increased their appeal, along with the capability of fine tuning the hardware design.…”

Section: Related Workmentioning

confidence: 99%

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

2020

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High Level Synthesis (HLS) tools targeting Field Programmable Gate Arrays (FPGAs) aim to provide a method for programming these devices via high-level abstractions. Initially, HLS support for FPGAs focused on compiling C/C++ to hardware circuits. This raised the issue of determining the programming practices which resulted in the best performing circuits. Recently, to further increase the applicability of HLS approaches, renewed effort was placed on support for HLS of OpenCL code for FPGA, raising the same issues of coding practices and performance portability. This paper explores the performance of OpenCL code compiled for FPGAs for different coding techniques. We evaluate the use of task-kernels versus NDRange kernels, data vectorization, the use of on-chip local memories, and data transfer optimizations by exploiting burst access inference. We present this exploration via a case study of the k-means algorithm, and produce a total of 10 OpenCL implementations of the kernel. To determine the effects of different data set characteristics, and to determine the gains from specialization based on number of attributes, we generated a total of 12 integer data sets. The data sets vary regarding the number of instances, number of attributes (i.e., features), and number of clusters. We also vary the number of processing cores, and present the resulting required resources and operating frequencies. Finally, we execute the same OpenCL code on a 4 GHz Intel i7-6700K CPU, showing that the FPGA achieves speedups up to 1.54× for four cases, and energy savings up to 80 % in all cases.

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Image Processing Using FPGAs

Cited by 22 publications

References 9 publications

A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs

A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs

A pre‐processing technique to decrease inspection time in glass tube production lines

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

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