Image Sensor with General Spatial Processing in a 3D Integrated Circuit Technology

Abstract

An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Abstract-An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.

Linear Current-Mode Active Pixel Sensor

“…The readout scheme is composed of two parts. The first part employs a second-generation current conveyor circuit (CCII+) [12]. This circuit is composed of a two-stage operational amplifier with a Miller compensation capacitor operated in a negative feedback mode via transistor M1.…”

“…Dark current shot noise power is proportional to integration time, as is the signal power; therefore the dynamic range (DR) remains constant regardless of integration time, as long as the reset noise dominates the dark current shot noise. This happens when the integration time is less than (12) The dark current was measured by resetting the pixels once and then reading multiple images in zero light. This measurement was repeated multiple times and the results were averaged.…”

“…The 0.18 m process implementation included a single 256 256 array of 10 10 m pixels. The authors have implemented the proposed pixel in two additional processes: 0.5 m 5 V CMOS [11] and 0.18 m 3-D integrated silicon-on-insulator [12].…”