A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel's design and operation, and presents an analysis of the pixel's temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 µm and a 1.8 V 0.18 µm CMOS process. The 0.35 µm process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 µm process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10 X 10 µm 2 , with fill factors of 26% and 66%, respectively. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Keywords CMOS analog integrated circuits, image sensors Disciplines Electrical and Computer EngineeringThis journal article is available at ScholarlyCommons: http://repository.upenn.edu/ese_papers/312

A single chip containing two 128×128 pixel imagers and currentmode disparity computation circuitry is described. Previous stereo vision sensors have not integrated computation circuitry [1] on the focal plane, or been limited to single depth values [2]. The previous single-chip stereo imager [3] used continuous-time imaging and computation circuits. These circuits were non-linear, power hungry, and had high levels of mismatch. They limited the operation of the previous chip, which was never equipped with optics to be able see an actual stereo pair, to very high-contrast scenes. The improvements of the chip described in this work include a more accurate computation block, the construction of optics, a 50% reduction in power consumption, and a linear current-mode imager with an uncorrected FPN that is lower than what has been reported for similar imagers [4].The algorithm described in [3], a simplified version of block matching using the sum of absolute difference (SAD) matching metric, is implemented on the chip. The output of the chip is the disparity ∆v between the left and right images of the stereo pair. For coplanar imagers (looking in the same direction) ∆v maps to depth z by z = bf / p∆v (where b: baseline, f: lens focal length, p: pixel pitch). Figure 27.8.1 shows a system diagram for the chip. For each location in the right image, the SAD metric for every candidate disparity in the left image is computed in parallel. The serial-scan parallel-computation architecture allows the chip to produce full-frame disparity maps (114×125 pixels) at 30frames/s while clocking the computation circuits at 430kHz. The chip also provides left and right image outputs and a spatial highpass of the right image, a match-validity-metric (MVM). The chip has a digital interface (excluding the image outputs) and can be used as a distance sensor without any external ADCs, DACs, or amplifiers.The integrating current-mode active pixel sensor (APS) implemented in the chip (Fig. 27.8.1) provides a linear conversion from light to output current [4]. The g m from the integrating node V pix to output current I pix is linearly adjustable by varying V col (3V nominal) as long as M2 is kept in the triode region. V reset is set at approximately |V tP | ≈ 0.8V below V DD , ensuring that M2 is always above threshold. Selecting multiple rows provides a vertical averaging (summation) of pixel values, as required by the algorithm. The imagers exhibit an uncorrected FPN of 1.2% (versus 1.9% and 0.8% before and after CDS in [4]). Readout circuits produce over half of this mismatch; the pixel FPN is calculated to be 0.9% which is low for a small (10µm pitch) and uncorrected current-mode pixel.

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A second-generation stereo vision chip, fabricated in right image and the left image is found as follows. The pixel values a 0.35gm 4M2P CMOS process and incorporating two 128 x in the block, size (15, N), around the coordinate (x, y) in the right 128 pixel linear current-mode imagers and current-mode image are vertically summed (1). The same is done for all possible disparity computation circuitry, is presented. Parallel target locations (x + d, y) in the left image (2). The SAD matching computation of the sum-of-absolute-difference matching metric for all candidate disparities d is computed (3). The candidate metric allows the chip to produce 114 x 124 pixel depth maps disparity in the search window D producing the smallest SAD value at 30 frames per second, performing 2.2 billion operations per is then deemed the disparity Ax (4). second, while using 10.1mA from a 3.3V supply.y+N-1 rm (x,y)=E R(x, j)(1) I.