Impact of Electrical Stress on Defect Generation in Thin GeO₂/Ge Gate Stacks Fabricated by Thermal Oxidation

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

“…Therefore, for SiGe material realize a high-quality IL between the high-k gate dielectric and SiGe channel by using the passivation process. Among the present passivation methods, such as thermal oxidation [8][9][10][11] and plasma treatment (O 2 , N 2 or NH 3 ) [12][13][14][15][16], in-situ ozone oxidation is considered the most promising strategy [17][18][19][20]. This is because it not only achieves a high-quality IL with an in-situ low thermal budget, but it is also more suitable for advanced three-dimensional devices, such as fin field effect transistors (FinFETs) or gate-all-around field effect transistors, due to its isotropic characterization [19,21].…”

A Comparative Study of AC Positive Bias Temperature Instability of Germanium nMOSFETs With GeO₂/Ge and Si-cap/Ge Gate Stack

“…Owning to the higher bulk mobility of both hole and electron, germanium (Ge) possesses great potential to replace silicon (Si) in the channel of CMOS to enhance the carrier transport and consequently to achieve higher drive currents and switching speeds [1]. Ge MOSFETs used to suffer from the lack of a good native oxide which results in massive interface states, but significant progress has been made recently [2][3][4][5][6][7][8][9][10][11][12]. After good initial performance was achieved, attention has been paid to device reliability to pave the way for the debut of Ge CMOS.…”