Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance

Bowman, Keith; Tang, Xizi; Eble, John; Menldl, J.D.

doi:10.1109/4.859508

Cited by 70 publications

(38 citation statements)

References 13 publications

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“…In this section, we use the template attacks introduced in [3], which are the most generic solution for this purpose 1 . Template attacks essentially work in two steps.…”

Section: Worst Case Scenario: Profiling and Attacking The Same Chipmentioning

confidence: 99%

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A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

Renauld

Standaert

Veyrat-Charvillon

et al. 2011

Lecture Notes in Computer Science

123

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Abstract. Variability is a central issue in deep submicron technologies, in which it becomes increasingly difficult to produce two chips with the same behavior. While the impact of variability is well understood from the microelectronic point of view, very few works investigated its significance for cryptographic implementations. This is an important concern as 65-nanometer and smaller technologies are soon going to equip an increasing number of security-enabled devices. Based on measurements performed on 20 prototype chips of an AES S-box, this paper provides the first comprehensive treatment of variability issues for side-channel attacks. We show that technology scaling implies important changes in terms of physical security. First, common leakage models (e.g. based on the Hamming weight of the manipulated data) are no longer valid as the size of transistors shrinks, even for standard CMOS circuits. This impacts both the evaluation of hardware countermeasures and formal works assuming that independent computations lead to independent leakage. Second, we discuss the consequences of variability for profiled side-channel attacks. We study the extend to which a leakage model that is carefully profiled for one device can lead to successful attacks against another device. We also define the perceived information to quantify this context, which generalizes the notion of mutual information with possibly degraded leakage models. Our results exhibit that existing side-channel attacks are not perfectly suited to this new context. They constitute an important step in better understanding the challenges raised by future technologies for the theory and practice of leakage resilient cryptography.

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“…In this section, we use the template attacks introduced in [3], which are the most generic solution for this purpose 1 . Template attacks essentially work in two steps.…”

Section: Worst Case Scenario: Profiling and Attacking The Same Chipmentioning

confidence: 99%

“…Second, device variability becomes important (i.e. it becomes increasingly difficult to engineer identical chips) [1,17]. As a consequence, the goal of this paper is to investigate the impact of these effects, with a focus on power variability, from the point of view of sidechannel attacks.…”

Section: Introductionmentioning

confidence: 99%

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

Renauld

Standaert

Veyrat-Charvillon

et al. 2011

Lecture Notes in Computer Science

123

View full text Add to dashboard Cite

show abstract

“…The effects of WID variations are becoming more and more prominent with scaling and they have a direct influence on local gate delay variations. Numerous random factors such as statistical deviations of the doping concentration and imprecision of lithography lead to more pronounced delay variations for minimum transistor sizes [13,14]. These factors are intrinsic since they cannot be eliminated by external control of conventional manufacturing.…”

Section: Minimizing Local Delay Variations For Nanoscale Cmos Technolmentioning

confidence: 99%

“…A large chip, however, contains many critical paths, all of which must satisfy the worst-case delay constraint [13][14][15][16]27]. For completely dependent paths (path delay correlation equal to 1), the PDF given in (3.11) is valid for all the paths to model the worst-case delay.…”

Section: Impact Of Within-die Variations On the Maximum Critical Pathmentioning

confidence: 99%

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

Jamaa

Kheradmand‐Boroujeni

Micheli

et al. 2009

Nanosystems Design and Technology

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“…With the progressive scaling of conventional MOSFETs to nanometre dimensions, variations in transistor characteristics due to random discrete dopants, interface roughness and line edge roughness start to adversely affect the yield and functionality of circuits constructed from them [1,2]. Due to the scaling limitations of the conventional MOSFETs, novel device architectures, such as UTB-SOI and multi-gate MOSFETs, that are also more resistant to some of the sources of intrinsic parameter fluctuations, are anticipated to play an increasingly important role before the end of the current ITRS [3] roadmap.…”

Section: Introductionmentioning

confidence: 99%

Combined sources of intrinsic parameter fluctuations in sub-25nm generation UTB-SOI MOSFETs: A statistical simulation study

Samsudin

Adamu-Lema

Brown

et al. 2007

Solid-State Electronics

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The ultra thin body (UTB) SOI architecture offers a promising option to extend MOSFET scaling. However, intrinsic parameter fluctuations still remain one of the major challenges for the ultimate scaling and integration of UTB-SOI MOSFETs. In this paper, using 3D statistical numerical simulations, we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of intrinsic parameter fluctuations in UTB-SOI MOSFETs. The sources of intrinsic parameter fluctuations, which can be separated in simulation, will occur simultaneously within a single MOSFET. To understand the impact of these sources of fluctuation in an actual device, simulations with all sources of intrinsic parameter fluctuations acting in combination have also been performed.

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Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance

Cited by 70 publications

References 13 publications

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

Combined sources of intrinsic parameter fluctuations in sub-25nm generation UTB-SOI MOSFETs: A statistical simulation study

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