Impact of Extrinsic Capacitances on FinFET RF Performance

Tinoco, J. C.; Rodriguez, Silvestre Salas; Martinez-Lopez, A. G.; Alvarado, J.; Raskin, Jean‐Pierre

doi:10.1109/tmtt.2012.2231697

Cited by 49 publications

(14 citation statements)

References 15 publications

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“…The significance of as revealed in Fig. 5 accords with the famous issue of Fin devices: Their RF performance is severely restricted by a relatively large inherently due to their three-dimensional gate structure [90]- [92]. In this regard, efforts have been made to boost the speed of Fin devices by decreasing , but note that such efforts essentially involve undesired degradation.…”

Section: A Srammentioning

confidence: 73%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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Section: A Srammentioning

confidence: 73%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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“…Also, the bias independent extrinsic series resistances R ge , R se , and R de are included. The intrinsic elements, which are parameters related to the physical phenomena inside the metal–oxide–semiconductor field-effect transistor (MOSFET) active region, depend on the geometry of the transistor and bias conditions [ 15 ]. The parasitic elements that surround the channel in order to get access to it are geometrically dependent but independent of the bias conditions.…”

Section: Asymmetric Dual-kk Trigate Finfet Structure and Performanmentioning

confidence: 99%

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit

et al. 2017

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Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.

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“…The layout of a FinFET critically impacts its highfrequency performance because of the layout's effect on the important parasitic series resistance and capacitance [12,13]. To investigate the RF performance of FinFETs, we have studied the performance of a test device (Fig.…”

Section: Layout Optimization Considering Parasitic Components Inmentioning

confidence: 99%

“…Such a model cannot reflect changes of fin height or RSD depth because TLM is only accurate when the current path in the junction is shallow. The radio-frequency (RF) performance of FinFETs has been investigated considering the parasitic series resistance and capacitance by widely varying its geometrical parameters [12,13].…”

Section: Introductionmentioning

confidence: 99%

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

An¹,

Choe²,

Kwon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (f T ). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.Index Terms-Cutoff frequency, fin field-effect transistors (FinFETs), fringe capacitance, number of gate fingers, number of fins, parasitic resistance, radio frequency (RF).

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Impact of Extrinsic Capacitances on FinFET RF Performance

Cited by 49 publications

References 15 publications

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

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