Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities

Akarvardar, K.; Young, C.D.; Baykan, Mehmet O.; Ok, I.; Ngai, T.; Ang, Kah‐Wee; Rodgers, Martin; Gausepohl, S. C.; Majhi, P.; Hobbs, Chris; Kirsch, P. D.; Jammy, R.

doi:10.1109/led.2011.2182603

Cited by 19 publications

(13 citation statements)

References 8 publications

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“…as-drawn fin-width is reduced to 70 nm. The presence of a hard mask on the top of the fin ensured double-gate instead of a trigate operation [5], [7]. The undoped Si layer that underlies the SiGe effectively decouples the device channel from the buried oxide [5], [7], consistent with the radiation response we report below.…”

Section: Methodssupporting

confidence: 80%

“…The presence of a hard mask on the top of the fin ensured double-gate instead of a trigate operation [5], [7]. The undoped Si layer that underlies the SiGe effectively decouples the device channel from the buried oxide [5], [7], consistent with the radiation response we report below. Unlidded devices were irradiated at a dose rate of 31.5 krad( )/min using a 10 keV ARACOR x-ray source, under positive, negative, and 0 V gate bias, with other terminals grounded, at room temperature.…”

Section: Methodssupporting

confidence: 80%

“…We first considered that the differences in radiation response with bias could be caused by differences in charge trapping in the buried oxide, as is commonly the case for triple-gate FinFET devices [14], [20], [21]. However, as discussed above, these devices are designed and fabricated to minimize the effects of both the top and back channels on device operation [5], [7], consistent with the curves in Fig. 2.…”

Section: Discussionmentioning

confidence: 92%

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Bias Dependence of Total Ionizing Dose Effects in SiGe-MOS FinFETs<formula formulatype="inline"> <tex Notation="TeX"/> </formula>

Duan

Zhang

et al. 2014

IEEE Trans. Nucl. Sci.

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The total ionizing dose (TID) response of double-gate SiGe-MOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the layer, in contrast to what is typically observed for devices with or gate dielectrics. This occurs in the devices because radiation-induced holes that are generated in the interfacial layer can transport and become trapped in the under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the interfacial layer can transport into the and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias.Index Terms-Double-gate FinFETs, , SiGe, threshold voltage shift, total ionizing dose.

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Section: Methodssupporting

confidence: 80%

Section: Methodssupporting

confidence: 80%

Section: Discussionmentioning

confidence: 92%

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Bias Dependence of Total Ionizing Dose Effects in SiGe-MOS FinFETs<formula formulatype="inline"> <tex Notation="TeX"/> </formula>

Duan

Zhang

et al. 2014

IEEE Trans. Nucl. Sci.

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“…2 of Ref. [4]) the measured 20 % decrease and 100 % mobility increase in N -type and P -type FinFETs [3,21], respectively, when the (100)/ 100 sidewall/channel configuration is rotated by 45 • around the wafer normal.…”

Section: Monte Carlo Modelmentioning

confidence: 97%

3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum correction

Bufler

Smith

2013

J Comput Electron

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The performance of FinFET and FDSOI devices is compared by 3D Monte Carlo simulation using an enhanced quantum correction scheme. This scheme has two new features: (i) the quantum correction is extracted from a 2D cross-section of the 3D device and (ii) in addition to using a modified oxide permittivity and a modified work function in subthreshold, the work function is ramped above threshold to a different value in the on-state. This approach improves the accuracy of the quantum-correction for multi-gate devices and is shown to accurately reproduce 3D density-gradient simulation also at short channel lengths. 15 nm FDSOI device performance with thin box and backgate bias is found to be competitive: compared to a Fin-FET with (110)/ 110 sidewall/channel orientation, the oncurrent for N -type devices is 25 % higher and the off-current is only increased by a factor of 2.5.

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“…INFET (fin-type field-effect transistor) has emerged as one of the best substitutes for planar MOSFET technology to enable further CMOS scaling. As shown in Fig.1, the FinFET device structure consists of a thin fin-shaped silicon body surrounded by shorted or independent gates on either side of the fin, constructed on SOI (silicon-on-insulator) [1]- [3] or bulk substrates [4], [5]. The FinFET device offers the following advantages [6]: 1) As the fin silicon body is generally thin enough with the thickness of the fin, denoted by T si , smaller than the channel length, denoted by L g , the gate electrode of the FinFET device has superior control over the channel, thereby suppressing the short-channel effects and leading to reduced subthreshold leakage, steeper subthreshold swing, and a higher I on /I off ratio; 2) As the thin silicon body of the FinFET device is typically undoped or lightly doped, the carrier mobility is thus enhanced with ionized dopant scattering eliminated, and the device variations due to random dopant fluctuation (RDF) are reduced.…”

Section: Introductionmentioning

confidence: 99%

Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs

Chang¹,

Wang

2016

ELS

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An independent-gate FinFET can operate in two modes: SG (shorted-gate) and IG (independent-gate) modes, and thus a FinFET-based circuit offers rich design options for lower power, better performance or reduced transistor count. In this paper, we present two novel dynamically power-gated FinFET TCAM cells, called DPG-17T and DPG-16T, which power-gate the prefix data storage unit when storing a ‘don't care’ value. With the dynamic power-gating mechanism, DPG 17T/DPG-16T achieve lower power dissipation by eliminating the switching power of the comparison FinFETs and suppressing the leakage power of the prefix data storage when storing a ‘don't care’ value. Moreover, the discharge path of the matchline in DPG-17T/DPG-16T can be constructed with only one FinFET instead of two FinFETs, greatly boosting the search speed. Simulation results have shown that a TCAM of 64-word×128-bit using DPG-17T/DPG-16T can reduce the worst-case search delay by 53.0%/53.6% and improve the energy-delay product by 68.5%/70.4% when operating under a search rate of 4.0 GHz.

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Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities

Cited by 19 publications

References 8 publications

Bias Dependence of Total Ionizing Dose Effects in SiGe-MOS FinFETs<formula formulatype="inline"> <tex Notation="TeX"/> </formula>

Bias Dependence of Total Ionizing Dose Effects in SiGe-MOS FinFETs<formula formulatype="inline"> <tex Notation="TeX"/> </formula>

3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum correction

Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs

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