Using a classification scheme based on carrier confinement type (electrostatic and spatial) and the degrees of freedom of the mobile carriers (3DOF, 2DOF, and 1DOF), strain effects on 3DOF to 1DOF silicon logic devices are compared from quantum confinement and device geometry perspectives. For these varied device geometries and types, the effects of strain-induced band splitting and band warping on the modification of the average conductivity effective mass and carrier scattering rates are evaluated. It is shown that the beneficial effects of strain-induced band splitting are the most effective for devices with little or no initial band splitting and become less so for devices with already large built-in band splitting. For these devices with large splitting energy, the potential for strain-induced carrier conductivity mass reduction through repopulation of lower energy bands and the suppression of optical intervalley phonon scattering are limited. On the other hand, for all devices without spatial confinement, a comparable amount of effective mass reduction occurs through favorable strain-induced band warping. Under spatial carrier confinement, much higher strain levels with respect to unconfined or electrically confined devices are required to observe strain-induced band warping in the band structure, with larger strain requirements as the confinement dimension decreases. In electrically confined volume-inversion devices, the favorable strain type required for carrier mass reduction results in increased surface scattering by bringing the carrier centroid closer to gate surfaces. However, for spatially confined volume-inversion devices, the favorable mechanical strain does not alter the carrier distribution in the device cross section. Consequently, strain is expected to be more effective in modification of low field carrier transport in electrically confined volume-inversion devices and less for spatially confined devices, with respect to conventional 2DOF planar metal-oxide-semiconductor field-effect transistors. On the other hand, for high-field quasiballistic transport, spatially confined devices, have the highest potential for strain-induced modification of device ballisticity, since the carrier backscattering ratio strongly depends on the surface roughness scattering rate at the source-end of the channel.

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The performance and reliability of doped and undoped (100)<100> and (110)<110> sidewall silicon-on-insulator (SOI) FinFETs with an Hf-based gate dielectric were evaluated. The electron mobility of the (110) FinFET sidewall is comparable to the (100) FinFET sidewall devices, which is opposite of the typical planar MOSFET electron mobility dependence on orientation, wherein (110) degrades significantly. In addition, TiN metal gate-induced strain cannot completely explain the similarity in (110) and (100) electron mobility because, although lower in magnitude, the two orientations with polysilicon electrodes resulted in similar mobility values. When investigating the orientation dependence of negative bias temperature instability (NBTI), (110) was found to cause more degradation than (100), and FinFETs with higher fin body doping demonstrated even more degradation.