(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs

Abstract

The performance and reliability of doped and undoped (100)<100> and (110)<110> sidewall silicon-on-insulator (SOI) FinFETs with an Hf-based gate dielectric were evaluated. The electron mobility of the (110) FinFET sidewall is comparable to the (100) FinFET sidewall devices, which is opposite of the typical planar MOSFET electron mobility dependence on orientation, wherein (110) degrades significantly. In addition, TiN metal gate-induced strain cannot completely explain the similarity in (110) and (100) electron mobility because, although lower in magnitude, the two orientations with polysilicon electrodes resulted in similar mobility values. When investigating the orientation dependence of negative bias temperature instability (NBTI), (110) was found to cause more degradation than (100), and FinFETs with higher fin body doping demonstrated even more degradation.

Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors

“…The hole wave-function is assumed to go to zero at the interface of the fin and the gate dielectric. The fin is considered to be uniformly p-type doped with a doping density of 2 Â 10 15 /cm 3 . Figure 4 summarizes the numerical simulation results for two fin widths of 20 nm and 60 nm-for the same values of V G used in the experiment.…”

“…Previous results show that the non-planar, fin-like structure and crystal orientation of the sidewalls can have an impact on performance and reliability. [2][3][4] Furthermore, the fin width can have a noticeable impact on threshold voltage, mobility, and reliability. [4][5][6] In current state-of-the-art technologies, negative bias temperature instability (NBTI) is a critical device degradation phenomenon that can be the limiting factor in device lifetime evaluation.…”

“…NBTI findings on surface orientation of FinFETs have shown that (110) surface can have slightly larger degree of degradation when compared to (100) surface. 2,3,7 Furthermore, similar to the scaling trends of conventional planar technologies, FinFETs must also reduce in dimension. Since the FinFET is currently being realized in mainstream production, understanding the implications of fin width scaling on the key aspects of reliability is necessary and requires thorough investigation.…”