Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

Semenov, O.; Pradzynski, A.H.; Sachdev, Manoj

doi:10.1109/66.983439

Cited by 40 publications

(5 citation statements)

References 27 publications

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“…The gate-induced drain leakage ͑GIDL͒ current is induced by the band-to-band tunneling effect in the strong accumulation mode and generated in the gate-to-drain overlap region in metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒. 1 The strong GIDL condition/or GIDL stress can introduce localized hot hole injection into the gate oxide and result in the instability of the device. Many efforts have been devoted to this field.…”

mentioning

confidence: 99%

Behaviors of gate induced drain leakage stress in lightly doped drain n-channel metal-oxide-semiconductor field-effect transistors

Cao

Gao

et al. 2009

Applied Physics Letters

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The behaviors of the gate induced drain leakage (GIDL) stress during the single and alternating stresses were investigated. A combination of threshold voltage Vth and GIDL current Igidl has been applied to investigate n-channel metal-oxide-semiconductor field-effect transistors with different gate oxide thicknesses. The recovery and enhancement of Vth depending on the gate oxide thickness, are found to result from the GIDL stress in the two processes. This study reveals that different behaviors of GIDL stress for different gate oxide thicknesses are attributed to the rivalship between the hole-induced carrier mobility increase and the interface states-induced increase in lightly doped drain resistance.

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mentioning

confidence: 99%

Behaviors of gate induced drain leakage stress in lightly doped drain n-channel metal-oxide-semiconductor field-effect transistors

Cao

Gao

et al. 2009

Applied Physics Letters

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“…The third component, GIDL current, is a strong function of transverse electric field at the semiconductor surface perpendicular to the device axis as given by (4) [22] (4) where (5) is a preexponential constant, is a physically based exponential parameter suggested by [23], is the drain-to-gate potential, is flatband voltage, and is the oxide thickness.…”

Section: A the Elements To Achieve Low Static Power Dissipation In Tmentioning

confidence: 99%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

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“…A is a pre-exponential constant; B is a physically based exponential parameter suggested by [24]; V DG is the drain-tosource potential; V FB is flatband voltage and t OX is the oxide thickness. Therefore, the overall leakage current can be reduced by decreasing the DIBL, t OX , the body doping concentration and the GIDL.…”

Section: Off Current Parametersmentioning

confidence: 99%

The design of a new spiking neuron using dual work function silicon nanowire transistors

Bindal¹,

Hamedi-Hagh²

2007

Nanotechnology

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A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 µW to generate a +1 V and 1.12 µW to generate a −1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 µm2.

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Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

Cited by 40 publications

References 27 publications

Behaviors of gate induced drain leakage stress in lightly doped drain n-channel metal-oxide-semiconductor field-effect transistors

Behaviors of gate induced drain leakage stress in lightly doped drain n-channel metal-oxide-semiconductor field-effect transistors

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

The design of a new spiking neuron using dual work function silicon nanowire transistors

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