Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

Jegadheesan, V.; Sivasankaran, K.; Konar, Aniruddha

doi:10.1016/j.mssp.2019.01.003

Cited by 49 publications

(24 citation statements)

References 28 publications

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“…(3) of [18]. But wider NS width (W NS ) allows to increase F t by enhanced G m of larger channel effective width [18]. As shown in Fig.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 94%

“…4a) and much larger R o (or much smaller drain conductance) in spite of smaller F t according to the eq. (5) of [18]. 3-CAS have the smallest F max because of the smallest F t and smaller output conductance in spite of similar C gd to 2-CAS.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 96%

“…Thus, the cascode devices have larger C gg and smaller G m , resulting smaller F t according to the eq. (3) of [18]. But wider NS width (W NS ) allows to increase F t by enhanced G m of larger channel effective width [18].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

See 2 more Smart Citations

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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“…(3) of [18]. But wider NS width (W NS ) allows to increase F t by enhanced G m of larger channel effective width [18]. As shown in Fig.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 94%

Section: Device Structure and Simulation Methodsmentioning

confidence: 96%

See 1 more Smart Citation

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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“…Vertically stacked Nanosheet transistors exhibit excellent ON-current density due to their increased effective width. The reference model of NS-FET with three layers having CPP of 48nm, the gate length of 12nm, and a sheet thickness of 5nm are simulated on a visual TCAD platform [21]. The inner spacer thickness and the width of NS-FET are kept at 5nm and 50nm respectively.…”

Section: Calibration Characteristicsmentioning

confidence: 99%

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Jain

Sawhney

Kumar

et al. 2021

Silicon

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In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10 -16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 10 11 has been achieved. The device exhibits a high transconductance of 3.022x10 -5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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“…But large gate resistance (R g ) from complex fin array structure and parasitic capacitance (C para ) limits the performance boosts of cutoff frequency (F t ) and maximum oscillation frequency (F max ) in the following technology node [12], [13]. Analog/RF performances of NSFETs have been investigated in terms of NS channel thickness (T NS ) and W NS for better analog/RF figure-of-merits (FoM) (G m R o , F t , F max ) [14]. But there are no qualitative analyses of analog/RF FoM and no explanations comparing to FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

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Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

Cited by 49 publications

References 28 publications

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

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