Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

Benbakhti, B.; Ayubi-Moak, J.S.; Kálna, K.; Lin, Dennis; Hellings, Geert; Brammertz, Guy; Meyer, K. De; Thayne, I.G.; Asenov, A.

doi:10.1016/j.microrel.2009.11.017

Cited by 26 publications

(12 citation statements)

References 12 publications

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“…15,16 However, the interface between the barrier layer and high-k oxide still plays an active role in device operation, having an impact on sub threshold swing 9 and the threshold voltage. 17 As such it is still necessary to characterize and investigate the surface and interface reactions that take place during surface preparations and after subsequent oxide depositions on this surface.…”

Section: Introductionmentioning

confidence: 99%

Chemical and electrical characterization of the HfO2/InAlAs interface

Brennan

Galatage

Thomas

et al. 2013

Journal of Applied Physics

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InAlAs has the potential to be used as a barrier layer in buried channel quantum well field effect transistor devices due to favorable lattice-matching and carrier confinement properties with InGaAs. Field effect device structures of this nature may also require a high-k oxide deposited on the InAlAs surface to reduce leakage current. This study investigates the impact of surface preparations and atomic layer deposition of HfO2 on these surfaces using x-ray photoelectron spectroscopy to analyse the chemical interactions taking place, as well as the electrical performance of associated capacitor devices. A large concentration of As related surface features is observed at the InAlAs surface, and is attributed to a large D-it response in electrical measurements. (C) 2013 AIP Publishing LLC

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Section: Introductionmentioning

confidence: 99%

Chemical and electrical characterization of the HfO2/InAlAs interface

Brennan

Galatage

Thomas

et al. 2013

Journal of Applied Physics

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“…Table 2 summarizes the material parameters used in our simulations [42,43]. According to the experimental findings, considerable amount of interface trapped charge density in the range of (2 Â 10 11 -4 Â 10 12 ) eV À1 cm À2 present at the heterostructure III-V channel/dielectric interface [44] is incorporated in our simulations [45]. Small signal ac simulation with 1 MHz frequency was used to extract various parasitic capacitances for the determination of cut-off frequency f T .…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

Chakraborty¹,

Sarkar

2015

Superlattices and Microstructures

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“…The intrinsic carrier concentration and the dielectric constant for InGaAs used in our study are 9×10 11 cm -3 and 14.63, respectively. Experimental findings have revealed that the InGaAs/high-k interface contains an appreciable amount of interface trap density in the range of 2×10 11 -4×10 12 eV -1 cm -2 [1,8]. Therefore, the interface-trapped-charge density is incorporated in the numerical device simulator ATLAS.…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Analog performance of dual-material gate InGaAs MOSFETs

Tewari

Biswas

Mallik

2012

2012 International Conference on Emerging Electronics

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Owing to large electron mobility, InGaAs MOSFETs show great promise for future high performance logic applications. Large dielectric constant of InGaAs, however, causes enhanced electrostatic coupling between the source and the drain that results in more pronounced short channel effects (SCEs), which in turn degrades the analog performance of such devices. A detailed investigation, with the help of a numerical device simulator, of the effects of using a dual-material gate (DMG) in such devices on its analog performance is reported for the first time in this paper. DMG devices are found to outperform their single-material gate counterparts in terms of transconductance, transconductance-to-drain current ratio, output conductance, intrinsic voltage gain, and unity-gain cut-off frequency.

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Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

Cited by 26 publications

References 12 publications

Chemical and electrical characterization of the HfO2/InAlAs interface

Chemical and electrical characterization of the HfO2/InAlAs interface

Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

Analog performance of dual-material gate InGaAs MOSFETs

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