Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs

Abstract

Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 µm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around L g = 50 nm.Index Terms-III-V, MOSFETs, quantum-well (QW), self-aligned.

Heterogeneous Integration of Atomically‐Thin Indium Tungsten Oxide Transistors for Low‐Power 3D Monolithic Complementary Inverter

“…Figure 3f illustrates that the R C of 2.5 nm and 4 nm channel thickness versus different V GS − V TH range from 1.5 to 3 V, in the step of 0.5 V. The contact resistance of Si MOSFET is typically increased by channel thickness thinning due to its parasitic resistance ( R parasitic ) generated from the source/drain (S/D) extension region [ 55 ] and the diminishment of diffusion length ( L T ). [ 56,57 ] In this work; however, it was observed that the R C in the a‐IWO TFT reduced with the thinning of the channel layer thickness. It may be contributed by the following two reasons: i) the reduction of channel R parasitic from the transistor structure, and ii) the gate‐induced Schottky barrier height (SBH) lowering.…”

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz fτ and 256 GHz f max

“…We report record f = 511 GHz for MOS-HEMT technology [1], [6]. While this technology has yet to surpass the maximum reported f of standard InP-based HEMTs [7], improvements in the access region design, optimization of channel design [8], and further scaling of the gate dielectric can further increase gm,e. Specifically, VLSI-optimized III-V MOSFETs have demonstrated extremely high gm,e of 3.0 mS/μm [9] and 3.45 mS/μm [10], even at the relatively small VDS = 0.5 V and small (VGS-VT) associated with VLSI operation; larger gm,e would be expected at larger voltages [1].…”

Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor

“…Scattering of alloy reduced, and better confinement of carrier, improved conductivity and mobility is observed by employing the cap layer on the top of heterostructure which proposed makes easy to fabric ohmic contact. A dual gate increases ID drain current and reduces leakage current, in turn, reflects on transconductance [20]. Silicon dioxide (SiO2), silicon carbide (6H-SiC), Si, and GaN of material with wide band gap semiconductors ultra-power microwave and radiofrequency application required material with high band gap [21].…”