Impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability of multicore real-time systems

Abstract

Based on the recent design trend from giant chipvendors, multicore systems are being deployed with multilevel caches to achieve higher levels of performance. Supporting real-time applications on multicore systems becomes a great challenge as caches are power hungry and caches make the execution time predictability worse. Studies show that timing predictability can be improved using cache locking techniques. However, level-1 (L1) entire locking may not be efficient if smaller amount of instructions/data compared to the cache size is locked. An alternative choice may be way locking. For some processors, way locking is possible at level-2 (L2) cache (not permitted at L1). Even though both L1 entire locking and L2 way locking improve predictability, it is difficult to justify the performance and power trade-off between these two locking mechanisms. In this work, we simulate a multicore system with two levels of caches to explore the impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability. Simulation results using FFT, DFT, and MPEG4 algorithms show that both performance and predictability can be increased and power consumption can be decreased by using a cache locking mechanism added to a cache memory hierarchy. Results also show that for FFT and DFT, L2 way locking outperforms L1 entire locking; but for MPEG4, L1 entire locking performs better than L2 way locking.

An efficient memory block selection strategy to improve the performance of cache memory subsystem

“…However, this method is not reliable; it may produce inaccurate results. The impact of I1 (level-1 instruction cache) entire locking and CL2 (level-2 cache) partial locking on the predictability of multicore real-time systems is studied in [1]. Experimental results show that for smaller code segments (like FFT), CL2 partial locking improves predictability more than I1 entire locking does; but for large applications (like MPEG4), I1 entire locking outperforms CL2 partial locking.…”

“…Cache locking is an important mechanism that adapts caches to the needs of real-time application processing. Recent studies show that the time required to perform a memory access is predictable with static/dynamic data/instruction cache locking [1][4] [5]. It is also observed that cache locking improves predictability by removing both intra-task and intertask interferences [6] [7].…”

“…Real-time application processing seriously su er due to the memory ine ciency from dropped frames, blocking, or other annoying artifacts [1] [2]. In order to support real-time and hard real-time processing cache memory hierarchy is changing.…”

Phase-based Cache Locking for Embedded Systems

“…Using simulations, Asaduzzaman et al [5] showed that cache locking could potentially improve cache performance and reduce power consumption. Yang et al [21] used a dynamic programming algorithm to determine the locked contents in order to improve the data cache's power consumption and performance.…”

Performance Implication of Multicore Cache Locking on General-Purpose Processors

“…For multicore processors, Suhendra et al [2] discussed the benefits of partition-based locking and compares core-and task-based partitioning. Asaduzzaman et al [3] studied L1 entire cache locking and L2 way-locking. Asaduzzaman et al [4] also used a miss table at the L2 cache level to dynamically and intelligently decide what cache blocks should and should not be locked based on the number of misses.…”