Impact of Large Gate Voltages and Ultrathin Polymer Electrolytes on Carrier Density in Electric-Double-Layer-Gated Two-Dimensional Crystal Transistors

Abstract

Electric-double-layer (EDL) gating can induce large capacitance densities (∼1−10 μF cm −2 ) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (V G ) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate and therefore the time scale over which the channel can be doped. Typical thicknesses are on the order of micrometers, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) in terms of both physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore quantum capacitance, is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied V G without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which V G is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3 × 10 13 cm −2 for electrons and 1.4 × 10 13 cm −2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, poly(ethylene oxide) (PEO):CsClO 4 , is decreased from 1 μm to 10 nm and used to EDL gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm−1 μm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.

Engineering an annular donor–acceptor reaction chamber with spontaneous feedstock collection for boosting CO2 photoreduction

“…Furthermore, Hall effect measurements were performed to investigate the density and transfer efficiency of carriers. 44,45 Driven by the Lorentz forces in the magnetic field, the photogenerated electrons and holes separate and converge in a plane perpendicular to both the magnetic field and current, exhibiting different Hall mobility depending on the catalysts. In Fig.…”

Strain-Induced 2H to 1T′ Phase Transition in Suspended MoTe2 Using Electric Double Layer Gating

“…Note that because V SG ≫ V DS in the voltage range where the phase transition is detected, the driving force for the phase change will primarily be provided by the V SG . Prior finite element modeling results show that applying a V DS of 0.5 V decreases the ion concentration near the drain contact by less than 2% …”

Tuning Gate Potential Profiles and Current–Voltage Characteristics of Polymer Electrolyte-Gated Transistors by Capacitance Engineering

“…A variety of different gate electrode architectures are used for polymer EGTs. − ,− In fact, one of attractive features of EGTs is that the gate electrode can be offset from the source-drain channel, which makes fabrication easier in some instances, albeit with a loss in switching speed. − ,,− , Gate electrode materials include metals such as Au, conducting polymers such as PEDOT:PSS as in Figure , and conducting porous carbon, for example. ,,− Often times, not much attention is paid to the size of the contact area between the gate and the electrolyte, despite a few previous studies indicating that the gate electrode significantly influences charge accumulation and EGT performance. − Here, we show that changing the gate–electrolyte contact area, which changes its interfacial capacitance, can have a profound impact on the measured current–voltage characteristics of EGTs. In fact, undersizing the gate electrode leads to large potential drops at the gate–electrolyte interface and produces drain current-gate voltage ( I D – V G ) curves that saturate at large V G ; it also causes large I D – V G hysteresis.…”