Electric-double-layer (EDL) gating can induce large capacitance densities (∼1−10 μF cm −2 ) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (V G ) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate and therefore the time scale over which the channel can be doped. Typical thicknesses are on the order of micrometers, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) in terms of both physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore quantum capacitance, is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied V G without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which V G is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3 × 10 13 cm −2 for electrons and 1.4 × 10 13 cm −2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, poly(ethylene oxide) (PEO):CsClO 4 , is decreased from 1 μm to 10 nm and used to EDL gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm−1 μm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.

Electric double layer (EDL) gating can induce large capacitance densities (∼1−10 μF/cm^2) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (VG) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate, and therefore the timescale over which the channel can be doped. Typical thicknesses are on the order of microns, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) both in terms of physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore, quantum capacitance is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied VG without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which VG is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3×10^13 cm^−2 for electrons and 1.4×10^13 cm^−2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, polyethylene oxide (PEO):CsClO_4, is decreased from 1 μm to 10 nm and used to EDL- gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm−1 μm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.