Impact of lateral source/drain abruptness on device performance

Abstract

This paper presents a detailed study of the impact of lateral doping abruptness in the source/drain extension region and the gate-extension overlap length on device performance. Proper choice of the metric used to compare the different device designs is essential. Series resistance and threshold voltage roll-offs are shown to be incomplete measures of device performance that could lead to inconsistent lateral abruptness requirements. While series resistance is seen to improve with increasing junction abruptness, threshold voltage roll-off could be degraded by both lateral junctions that are too gradual and too abrupt-in contrast to the conventional scaling assumptions. The on (supernominal)-o (subnominal) plot, which takes into account statistical variations of gate length, is proposed as a good metric for comparing different device technology designs. Gate-extension overlap length is shown to interact with lateral doping abruptness and to have a significant impact on device performance.

Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

“…This problem is even more severe in a DGFET since the presence of two channels implies that twice the current flows through the series resistance, leading to higher potential drop across the extrinsic resistance. Previous work on analysis [9], [10] of extrinsic resistance has been Manuscript received July 23, 2003; revised August 15, 2003 focused on the conventional planar bulk MOSFET structure. In [10], the authors suggest the existence of optimal lateral abruptness of the source/drain extension doping profile.…”

“…Previous work on analysis [9], [10] of extrinsic resistance has been Manuscript received July 23, 2003; revised August 15, 2003 focused on the conventional planar bulk MOSFET structure. In [10], the authors suggest the existence of optimal lateral abruptness of the source/drain extension doping profile. It is not clear whether the same results and conclusions would hold for advanced ultrathin body DGFET structures where the process constraints and tunable parameters are quite different.…”

Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement

“…Further device simulation suggests that with the junction abruptness improved from the original 10dec/nm to the ITRS requested 2.7dec/nm [9] for a 50nm channel length, the peak f T within gate bias of 1.5V can reach as high as 99.4GHz. This corresponds to an almost threegeneration-hop in RF performance that can be ultimately achieved with VMOSFETs using a 0.35µm lithography stepper if ultra abrupt junctions are achieved by advanced annealing techniques.…”

Variability-Aware Device Optimization under ION and Leakage Current Constraints

“…For example, the short channel effects have been found to be independent of the junction depth Yj and simulation results showed that IoN increases significantly with the increase in Yj [6]. Additionally, a detailed study of the impact of lateral doping abruptness of SDE on device's ION and IOFF was presented in [7] and proposed some design guidelines for the SDE. Also, leakage currents have been shown to be more sensitive to the variations in T0,o Halo doping profile (Nhalo, lC), and Lg [4].…”