Impact of line width roughness on device performance

Lorusso, Gian; Leunissen, L. H. A.; Gustin, C.; Mercha, A.; Jurczak, M.; Marchman, Herschel M.; Azordegan, A.

doi:10.1117/12.656128

Cited by 18 publications

(8 citation statements)

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“…They also control the partition of R q (L→∞) to R q (L) and CD variation as the line length L reduces since it has been shown that the sum of the average values of the squares of the R q and CD variation for any line length L is independent of L and equal to the square of R q (L→∞) (see Fig.1) [15][16][17] . In the contribution of our group in previous SPIE conferences, we examined mainly the role of the correlation length ξ and its impact on threshold voltage shift and deviations from the nominal values 18,19 . In particular, we showed that resist lines with lower correlation lengths lead to transistors with threshold voltage nearer to the nominal value.…”

Section: Introductionmentioning

confidence: 99%

Fractal dimension of line width roughness and its effects on transistor performance

Constantoudis¹,

Gogolides²

2008

SPIE Proceedings

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The effects of Line Width Roughness (LWR) on transistor performance are one of the hottest issues in semiconductor industry. However, in most related studies, LWR is considered as the fluctuations of gate lengths and not of resist lines. In this paper, we examine the direct effects of one of the spatial resist LWR parameters, the fractal dimension, on transistor off current deviations for various correlation lengths and gate widths. The aim is to exploit the fractality of LWR in order to link the gap between the LWR of long resist lines and the gate length roughness that affects transistor performance. The used methodology is based on the simulation of both resist lines and transistor operation. The results of the two step methodology are presented for both narrow and wide gates. For the first, it is found that for all correlation lengths, higher fractal dimension (smaller roughness exponent) of the resist line leads to off state currents closer to the nominal value. For wide gates, an interesting differentiation is found at the dependence of the standard deviation from the fractal dimension as correlation length decreases. For sufficiently low correlation length, the behavior is reversed and the low fractal dimension are more beneficial that the higher ones. An explanation of that reverse is provided by means of the dependence of the CD variation on gate width for various fractal dimensions. Finally, the implications of these findings on the dependencies of the yield of transistors on fractal dimension and correlation length are also discussed.

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Section: Introductionmentioning

confidence: 99%

Fractal dimension of line width roughness and its effects on transistor performance

Constantoudis¹,

Gogolides²

2008

SPIE Proceedings

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“…[10][11][12][13][14][15] Another factor is line edge roughness ͑LER͒. [16][17][18][19] The edges of patterned fine lines are not straight but irregularly winding, and the line width randomly fluctuates as a result. The width variation is sometimes called line width roughness ͑LWR͒ similarly to LER.…”

Section: Introductionmentioning

confidence: 99%

Discrete power spectrum of line width roughness

Hiraiwa

Nishida

2009

Journal of Applied Physics

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The variation of device characteristics is a challenge to present and future large-scale integrations. One of the origins of the variation is line width roughness (LWR). To facilitate the efforts to cope with LWR, we developed a method to accurately characterize LWR basing on the analysis of power spectral densities (PSDs). Because experimental PSDs are intrinsically discrete, we derive simple analytic formulas of the discrete PSDs by assuming that the autocorrelation function (ACF) exponentially decays with distance. The PSDs calculated by using the formulas agree excellently with experimentally obtained PSDs of photoresist LWR. From the result we find that the photoresist LWR of this study has a standard deviation of 2.5 nm and an exponentially-decaying autocorrelation function with a correlation length of 35 nm. Although the experimental PSDs inevitably contain a component produced by scanning-electron-microscope (SEM)-image noise, the two components of LWR and noise are separately determined by the method of this study. Due to this feature, the resultant variance of LWR is independent of the noise intensity. However, it is still important to reduce the noise component in order to maintain the accuracy of analysis especially in the case of LWR that has an unknown functional form of PSD. This is because even the PSDs that have different functional forms sometimes look alike in the presence of large noise. To reduce the noise effect, it is effective to average the SEM images perpendicularly to fine lines before edge detections. The procedure does not reduce the variance unlike averaging along the lines. The method of this study is applicable not only to LWR but also to other cases as far as the ACF exponentially decays with distance, or equivalently the spectral line shape is Lorentzian. Accordingly, it forms the basis for spectral analysis of most experimental results.

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“…In the lithographic community, LWR is defined as the deviations of the widths of fabricated resist lines from their nominal CD value 1-4 . The usual argument for its increasing importance in the near future of IC manufacturing is that as the dimensions of the nominal gate CD values are reduced it will start to affect the electrical performance of the transistor [5][6][7][8][9][10][11][12] . Although the main point of this argument is correct, a clarification is needed.…”

Section: Introductionmentioning

confidence: 99%

Correlation length and the problem of line width roughness

2007

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The Line Width Roughness (LWR) measured by lithographers usually refers to long resist lines. On the contrary, the transferred roughness in the transistor gate (Gate Length Roughness, GLR) which is one eventually affecting transistor performance is associated with short gate widths equal to only a few multiples of CD values. Given that the most basic roughness metric, r.m.s. value R q (or sigma), depends on the sample length at which is measured, the issue of the metrological relationship between resist (or lithographic) LWR and transistor GLR arises. The LWR parameter which seems to link these two kinds of roughness is the correlation length, since it determines the form of the curve R q (L) describing the dependence of r.m.s. value on line length L. This paper investigates three issues relating to correlation length. The first is the precision of its measurement and it is found that the relative standard deviation of the measured values can become less than 25% provided that sufficient line lengths are included in the measurement process. Further, the measurement uncertainty is reduced when lower correlation lengths are measured. Secondly, we examine the importance of the correlation length to the electrical transistor performance and show that lower correlation lengths increase noticeably the fraction of good transistors with reliable small voltage threshold shifts independent on the used technology node and gate width. Finally, the material and process origins of correlation length variations are investigated in order to locate the appropriate changes for reducing correlation length.

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Impact of line width roughness on device performance

Cited by 18 publications

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Fractal dimension of line width roughness and its effects on transistor performance

Fractal dimension of line width roughness and its effects on transistor performance

Discrete power spectrum of line width roughness

Correlation length and the problem of line width roughness

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