Fractal dimension of line width roughness and its effects on transistor performance

Abstract

The effects of Line Width Roughness (LWR) on transistor performance are one of the hottest issues in semiconductor industry. However, in most related studies, LWR is considered as the fluctuations of gate lengths and not of resist lines. In this paper, we examine the direct effects of one of the spatial resist LWR parameters, the fractal dimension, on transistor off current deviations for various correlation lengths and gate widths. The aim is to exploit the fractality of LWR in order to link the gap between the LWR of long resist lines and the gate length roughness that affects transistor performance. The used methodology is based on the simulation of both resist lines and transistor operation. The results of the two step methodology are presented for both narrow and wide gates. For the first, it is found that for all correlation lengths, higher fractal dimension (smaller roughness exponent) of the resist line leads to off state currents closer to the nominal value. For wide gates, an interesting differentiation is found at the dependence of the standard deviation from the fractal dimension as correlation length decreases. For sufficiently low correlation length, the behavior is reversed and the low fractal dimension are more beneficial that the higher ones. An explanation of that reverse is provided by means of the dependence of the CD variation on gate width for various fractal dimensions. Finally, the implications of these findings on the dependencies of the yield of transistors on fractal dimension and correlation length are also discussed.

Line Width Roughness effects on device performance: The role of the gate width design

“…The main findings of the paper are summarized in the final Section VI. In previous works of our group [5]- [7], we have shown that for fixed design transistor parameters, the lowering of the spatial LWR parameters of the manufactured long lines improves the reliability of the fabricated transistors. The present work completes this finding by examining the role of a basic design parameter in the LWR degradation effects on transistor operation.…”

Noise-free estimation of spatial line edge/width roughness parameters

“…Thus the connection of lithographic LER/LWR studies with GLR effects on transistor performance pass through the examination of spatial LER/LWR parameters ξ,α. In this context, we have evaluated the effects of lithographic ξ,α on transistor performance and presented the results in previous contributions of our group to SPIE [9][10][11]. The main finding was that correlation length affects mainly the deviations from the nominal threshold voltage of a planar MOSFET, while the off state leakage current is more sensitive to changes of the roughness exponent.…”

Sidewall roughness in nanolithography: origins, metrology and device effects

“…As referred to in Section 16.2.2, resist LWR (rms value) has been agreed to be measured in lines longer than 2 μ m (Constantoudis et al ., 2004;;Leunissen et al ., 2004;Yamaguchi et al ., 2005;Patsis et al ., 2006;Constantoudis and Gogolides, 2008;Constantoudis et al ., 2012.). On the other hand, GLR is defi ned in lengths equal to the gate widths, which are usually some multiples of CD (~20-40 nm) i.e much shorter than 2 μ m. Given the dependence of rms value on edge length (see Section 16.2.2), this length difference translates to differences in the rms values of LWR and GLR.…”

“…One can notice the sharing of resist LWR of long lines into GLR and CD variation as well as the critical role of the spatial LWR parameters ( ξ , α ) in the control of this partition(Constantoudis and Gogolides, 2008). Dependence of the average threshold voltage shift δ V th (a), the standard deviation σ ( δ V th ) (b), the average I off / I off,ideal (c) and the standard deviation σ ( I off / I off,ideal ) on the spatial LWR parameters α , ξ .…”