Line Width Roughness effects on device performance: The role of the gate width design

Abstract

The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. Exploiting the implications of these results through a 2D modeling approach, we indicate that, for fixed LWR, transistors with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.

Determining the validity domain of roughness measurements as a function of CD-SEM acquisition conditions

“…Stochastic effects are growing in importance as the feature dimensions are being reduced. Monitoring those effects is part of the challenges for continuously enabling the advances in semiconductor resolution limits and benefit from the scaling effects [1]. One of the significant stochastic effects is within-feature roughness.…”

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In the effort of continuously improving patterning strategies for increasing circuit density while reducing dimensions, several challenges regarding patterning fidelity emerge. In recent years, stochastic effects had their relative importance increased, and therefore the need for closely monitoring those effects is also increasing [1]. Among other stochastic effects, within-feature roughness is significant as it can impact circuit electrical behavior, decreasing time and power performance, and even lead to failures.

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