Sidewall roughness in nanolithography: origins, metrology and device effects

Impact of Line Edge Roughness on ReRAM Uniformity and Scaling

“…Here, c is the c-factor quantifying the cross-correlations between the left and right edges of lines. For totally uncorrelated edges, c = 0, whereas for fully correlated (anti-correlated), c = 1 (−1) [26,33]. By combining (2), (3), and (4) we read:σ(Α)=2〈CDi〉 (1−c)false(rmsLER2(total)−<rmsLER2(CDifalse)>).…”

“…However, quite early, the characterization scheme was enriched with more parameters and functions aiming to capture and quantify the spatial/lateral or frequency aspects of LER preserving the dominant significance of rms. To this end, a three-parameter model has been proposed [26] consisting of rms value, correlation length ξ, and roughness exponent α (related to the fractal dimension d = 2− α ) and extensively used in different applications. The first parameter rms quantifies the vertical aspects of LER and is calculated by the standard deviation of the edge points about their mean value.…”

“…This effect has underlined the importance of estimating the PS of LWR, which quantifies the contribution to LWR from different frequency areas. A detailed presentation of the conventional LER and LWR metrology can be found in [26].…”

“…LER is actually the sidewall roughness of pattern lines manufactured via standard lithographic rules, as often observed via top-down SEM images. The effect of LER becomes more evident as the size of devices is reduced, which is the reason for the recent upsurge of interest in LER control in modern <20 nm semiconductor manufacturing [26]. Obviously, LER is responsible for the area variability of devices in a crossbar (Xbar) array and, furthermore, the cell-to-cell and wafer-to-wafer variability that appear in the operation parameters of ReRAM memory cells in Xbar arrays.…”