Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Shubhakar, K.; Raghavan, Nagarajan; Kushvaha, S. S.; Bosman, Michel; Wang, Zhongrui; O’Shea, S. J.; Pey, K. L.

doi:10.1016/j.microrel.2014.07.154

Cited by 10 publications

(7 citation statements)

References 15 publications

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“…These differences could be explained because up to now, only differences in depth and geometry surface have been considered and the simulation has not taken into account the HfO 2 -SiO 2 and SiO 2 -substrate roughnesses. Other effects, such as the presence of traps in the high-k dielectric (not included yet in the simulator) that could favor Trap Assisted Tunneling through GBs, or different electrical properties between grain and GBs, 17 also could explain the observed differences between the experimental data and the simulations. In fact, in one study, CAFM experimental data and a simulation model that considered different dielectric constants for grains and GBs were used to demonstrate that the faster degradation observed at GBs in HfO 2 /SiO x stacks could be attributed to an enhanced electric field across the SiO x layer beneath the thinner HfO 2 film at these sites.…”

Section: A Topography Resultsmentioning

confidence: 99%

Conductive-AFM topography and current maps simulator for the study of polycrystalline high-k dielectrics

Couso

Porti

Martín-Martínez

et al. 2015

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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In this work, a simulator of Conductive Atomic Force Microscopy (C-AFM) was developed to reproduce topography and current maps. In order to test the results, we used the simulator to investigate the influence of the C-AFM tip on topography measurements of polycrystalline high-k dielectrics, and compared the results with experimental data.The results show that this tool can produce topography images with the same morphological characteristics as the experimental samples under study. Additionally, the current at each location of the dielectric stack was calculated. The Quantum Mechanical Transmission Coefficient (QMTC) and tunneling current were obtained from the band diagram by applying the Airy wavefunction approach. Good agreement between experimental and simulation results indicates that the tool can be very useful for evaluating how the experimental parameters influence C-AFM measurements.

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Section: A Topography Resultsmentioning

confidence: 99%

Conductive-AFM topography and current maps simulator for the study of polycrystalline high-k dielectrics

Couso

Porti

Martín-Martínez

et al. 2015

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…Yet, amongst all these issues, the interface properties and their thermal instabilities need to be resolved firstly [64][65][66][67][68][69][70][71][72]. Transition metal (TM) or rare-earth metal (RE) based high-k dielectrics are extrinsic materials to the substrate silicon.…”

Section: Subnanometer Eot Leakage Current and High-k Instabilitiesmentioning

confidence: 99%

“…It was proposed that the oxygen in W may diffuse into the La 2 O 3 film to fill up the oxygen vacancies there. Oxygen vacancies are the major defect centers in La 2 O 3 which result in several instability issues and enhance the gate leakage current [59][60][61][62][63][64][65][66][67][68][69][70][71]. Post-metallization annealing may cause an reverse effect.…”

Section: Lanthanum Oxide/metal Gate Interfacementioning

confidence: 99%

“…Most of the high-k silicides are conductive. The interfacial silicide layer would not affect the EOT but the interface metal-Si bonding is one of the interface trap precursors and results in the channel mobility degradation and in other instabilities [2,[59][60][61][62][63][64][65][66][67][68][69][70]. Most of the high-k materials, including hafnium oxide and lanthanum oxide are only marginally stable against the formation of silicates.…”

Section: Lanthanum Oxide/silicon Interfacementioning

confidence: 99%

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On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Wong

Iwai

2015

Microelectronic Engineering

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“…For instance, to limit the gate leakage current, ultra-thin Silicon Dioxide (SiO2) gate oxide has been replaced by high-k dielectrics [2]. However, some high-k materials show a polycrystalline structure [3], [4], which could affect the electrical properties of scaled devices [5] by increasing the leakage current and the deviceto-device variability. Since high-k polycrystallization takes place at the nanometer scale [4], Conductive Atomic Force Microscopy (C-AFM) has been demonstrated to be a very powerful technique to evaluate at the suitable scale the morphological and electrical properties [6]- [10] of polycrystalline high-k dielectrics [11]- [15].…”

Section: Introductionmentioning

confidence: 99%

Methodology for the Simulation of the Variability of MOSFETs With Polycrystalline High-k Dielectrics Using CAFM Input Data

et al. 2021

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In this work, a simulation methodology, whose inputs are Conductive Atomic Force Microscope (CAFM) experimental data, is proposed to evaluate the impact of nanoscale variability sources related to the polycrystallization of high-k dielectrics (i.e., oxide thickness, tox, and charge density, ρox, fluctuations in the nanometer range) on the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) variability. To simulate this variability, a Thickness And Charge MAp Generator (TACMAG) has been developed and used in combination with an in-house-built 3D device simulator (VENDES). From CAFM experimental data (topography and current) obtained on a small area of a given polycrystalline dielectric, the TACMAG generates a high amount of tox and ρox configurations of the gate dielectric, with identical statistical characteristics to those experimentally measured. These dielectrics are then introduced into the device simulator, with which the impact of the tox and ρox fluctuations in the dielectric on the variability of MOSFETs (i.e., threshold voltage) is analyzed. The proposed methodology has been verified by comparing the Vth variability of MOSFETs whose dielectric properties were generated with TACMAG to other devices whose gate oxide characteristics have been determined experimentally with CAFM. Finally, it has been used to analyze the impact of different nanoscale parameters, such as the Grain size and Grain Boundaries depth (of polycrystalline dielectrics) on such variability.

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Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Cited by 10 publications

References 15 publications

Conductive-AFM topography and current maps simulator for the study of polycrystalline high-k dielectrics

Conductive-AFM topography and current maps simulator for the study of polycrystalline high-k dielectrics

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Methodology for the Simulation of the Variability of MOSFETs With Polycrystalline High-k Dielectrics Using CAFM Input Data

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