Impact of Memory Architecture on FPGA Energy Consumption

Abstract

FPGAs have the advantage that a single component can be configured post-fabrication to implement almost any computation. However, designing a one-size-fits-all memory architecture causes an inherent mismatch between the needs of the application and the memory sizes and placement on the architecture. Nonetheless, we show that an energybalanced design for FPGA memory architecture (memory block size(s), memory banking, and spacing between memory banks) can guarantee that the energy is always within a factor of 2 of the optimally-matched architecture. On a combination of the VTR 7 benchmarks and a set of tunable benchmarks, we show that an architecture with internallybanked 8Kb and 256Kb memory blocks has a 31% worstcase energy overhead (8% geomean). In contrast, monolithic 16Kb memories (comparable to 18Kb and 20Kb memories used in commercial FPGAs) have a 147% worst-case energy overhead (24% geomean). Furthermore, on benchmarks where we can tune the parallelism in the implementation to improve energy (FFT, Matrix-Multiply, GMM, Sort, Window Filter), we show that we can reduce the energy overhead by another 13% (25% for the geomean).

Monolithic 3-D FPGAs

“…In today's FPGAs, the block RAM is usually included. The block RAM's memory architecture, which includes block sizes, banking, and spacing, has been optimized to improve energy efficiency [88], but the extent is still limited by the geometry of a logic tile in 2-D. With memory and logic placed on different layers in 3-D, the architecture and (b) five-metal-layer (marked as ''M1'' to ''M5'') CMOS logic circuits and RRAM-based configuration memory (marked as ''programmable resistor'' in the image) [86]; and (c) five-metal-layer CMOS logic circuits, Ge PMOS pass transistors, and RRAM-based configuration memory [29]. placement of each can be tuned separately to achieve further performance improvement.…”

Impact of Parallelism and Memory Architecture on FPGA Communication Energy

“…Since our logic block is smaller, our energy minimizing cases tend to place the memories more frequently than the commercial architectures, closer to the robust balance point identified analytically in Section 3. In Kadric et al [2015], we also explored architectures with two memory sizes and found that without internal banking, they achieved a similar reduction in worst-case overhead to one memory with internal banking. Combining internal banking and two memory sizes can further reduce energy overheads at the expense of higher area.…”

“…For example, if we had both 1Kb and 64Kb memories, we could map the 2Kb and smaller application memories to the 1Kb memory block and the 4Kb and larger application memories to the 64Kb block and reduce the worst-case overhead to 1.1× (Figure 3(a)). The impact of multiple memory sizes is explored experimentally in Kadric et al [2015]. Another point of mismatch between architecture and application is the width of the data written or read from the memory block.…”

“…-Analytic characterization of the energy-optimal level of parallelism for applications (Section 2) -Analytic characterization of the energy overhead that results from mismatches between the logical memory organization needed by a task and the physical memory organization provided by an FPGA (Section 3) -Introduction of the continuous hierarchy memory (Section 3) and characterization of its benefits (Section 7) -Characterization of how parallelism impacts energy consumption, including demonstration of how parallelism tuning can reduce energy (Section 6) -First empirical exploration of memory architecture space for energy minimization (Section 7) -VTR-compatible memory mapping for energy minimization (Section 5.2) This article is a unification and expansion of Kadric et al [2014Kadric et al [ , 2015. The analysis for parallel scaling (Section 2.3) is new.…”

“…The analytic bounds on memory mismatch overhead have been tightened using the golden ratio layout (Section 3). This article includes the effects of width mismatch, which were omitted in Kadric et al [2015], and the parallelism benchmark set has been expanded beyond [Kadric et al 2014]. We omit parallel mappings to commercial architectures (included in Kadric et al [2014]) and the treatment of multiple memory sizes (included in Kadric et al [2015]).…”